Commit Graph

5 Commits

Author SHA1 Message Date
Elaine Zhang
00e6751ffc clk: rockchip: add sclk_timer5 as critical clock on rk3128
sclk_timer5 is for arm arch counter, so need always on.
but no dts node to handle this clk, so make it as critical clock

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-09-17 01:55:36 +02:00
Elaine Zhang
a4eb286565 clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs error
A copy-paste error made them use the wrong bits in the register.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-09-17 01:55:36 +02:00
Elaine Zhang
e8620acc90 clk: rockchip: add pclk_pmu as critical clock on rk3128
pclk_pmu need always on, and no dts node to handle this clk,
so make it as critical clock

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-09-17 01:55:36 +02:00
Elaine Zhang
3346140588 clk: rockchip: modify rk3128 clk driver to also support rk3126
rk3128 and rk3126 have some gate registers describe differences.
So need to make some distinctions.
The RK3126 and RK3128 Same clock description we move it to
the common clock branches.
And the different clks description use the own clock branches.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-08 17:30:29 +02:00
Elaine Zhang
f6022e88fa clk: rockchip: add clock controller for rk3128
Add the clock tree definition for the new rk3128 SoC.
And it also applies to the RK3126 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02 14:49:35 +02:00