Commit Graph

27 Commits

Author SHA1 Message Date
David Zhang
af15a2d51d drm/amdgpu: Add Fiji support to the GFX 8.0 IP module (v2)
v2: agd5f: fix the rb setup.

Signed-off-by: David Zhang <david1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-17 16:50:27 -04:00
Jammy Zhou
2f7d10b393 drm/amdgpu: merge amdgpu_family.h into amd_shared.h (v2)
Make the definitions common for all driver components

v2: fix kfd

Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-17 16:50:21 -04:00
Alex Deucher
b8826b0cbf Revert "drm/amdgpu: Configure doorbell to maximum slots"
This reverts commit 78ad5cdd21.
This commit breaks dpm and suspend/resume on CZ.
2015-08-12 12:24:04 -04:00
Jammy Zhou
595fd013f7 drm/amdgpu: set fw_version and feature_version for smu fw loading
The fw_version and feature_verion should be set correctly when the
firmwares are loaded by SMU on Tonga/Carrzio/Iceland

Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-05 14:26:50 -04:00
Jammy Zhou
351643d7dd drm/amdgpu: add feature version for RLC and MEC v2
Expose feature version to user space for RLC/MEC/MEC2 ucode as well

v2: fix coding style

Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-05 14:26:49 -04:00
Alex Deucher
a0e2f50bdb drm/amdgpu: fix rb setting for CZ
Always set num_rbs to 2 for CZ.  The 1 RB parts are often harvest
configs.  The will get sorted out in mesa when we program
PA_SC_RASTER_CONFIG[_1].

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-05 14:26:48 -04:00
monk.liu
93323131d6 drm/amdgpu: different emit_ib for gfx and compute
compute ring didn't use const engine byfar, so ignore CE things in
compute routine

Signed-off-by: monk.liu <monk.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-07-29 16:05:57 -04:00
Alex Deucher
4f2d3ad686 drm/amdgpu: remove bogus check in gfx8 rb setup
Always respect the harvest configuration as is.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-07-16 12:39:41 -04:00
Sonny Jiang
845253e78a drm/amdgpu: reset wptr at cp compute resume (v2)
This patch is to resolve compute hang at resume time.

v2: (agd5f) squash in second fix

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-06-29 11:21:48 -04:00
Ben Goz
78ad5cdd21 drm/amdgpu: Configure doorbell to maximum slots
Signed-off-by: Ben Goz <ben.goz@amd.com>
Acked-by: Oded Gabbay <oded.gabbay@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-29 11:21:40 -04:00
Ben Goz
cd06bf687b drm/amdgpu: Initialize compute sdma and memory from kgd
v2: add missing MTYPE_NONCACHED enum

Signed-off-by: Ben Goz <ben.goz@amd.com>
Acked-by: Oded Gabbay <oded.gabbay@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-29 11:21:39 -04:00
Alex Deucher
6a00a09e49 drm/amdgpu: update to latest gfx8 golden register settings
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-10 09:13:35 -04:00
David Zhang
147dbfbc54 drm/amdgpu: remove the VI hardware semaphore in ring sync
Signed-off-by: David Zhang <david1.zhang@amd.com>

Reviewed-by: Christian König <christian.koenig@amd.com>
2015-06-10 09:06:45 -04:00
Alex Deucher
bd5c97bc1a drm/amdgpu: set the gfx config properly for all CZ variants (v2)
Need to adjust the number of CUs and RBs.

v2: get proper values

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Samuel Li <samuel.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-08 21:42:54 -04:00
Chunming Zhou
890ee23fc6 drm/amdgpu: disable user fence interrupt (v2)
amdgpu submits both kernel and user fences, but just need one interrupt,
disable user fence interrupt and don't effect user fence.

v2: fix merge error

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-05 11:02:06 -04:00
Ken Wang
02558a006c drm/amdgpu: add me/ce/pfp_feature_version interface query
Provide this information to usermode drivers.  We were previously
missing this info.

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-06-03 21:04:02 -04:00
Ken Wang
a101a8995a drm/amdgpu add ce_ram_size for interface query
Add a query for the CE ram size.  User mode drivers
will want to use this to determine how much size
of the cache on the CE.

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewd-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-06-03 21:04:02 -04:00
monk.liu
35074d2d40 drm/amdgpu: add hdp flush for gfx8 compute ring
We had forgotten to register the callback.

Signed-off-by: monk.liu <monk.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: jammy zhou <jammy.zhou@amd.com>
2015-06-03 21:04:00 -04:00
monk.liu
b9a7faaeb2 drm/amdgpu: remove all sh mem register modification in vm flush
Leave that at the values set during init.  No need to update
them repeatedly.

Signed-off-by: monk.liu <monk.liu@amd.com>
Signed-off-by: David Zhang <david1.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jammy Zhou <jammy.zhou@amd.com>
2015-06-03 21:03:56 -04:00
yanyang1
5fc3aeeb9e drm/amdgpu: rename amdgpu_ip_funcs to amd_ip_funcs (v2)
The structure is renamed and moved to amd_shared.h to make
the component independent.  This makes it easier to add
new components in the future.

v2: fix include path

Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: yanyang1 <young.yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03 21:03:51 -04:00
Jammy Zhou
c65444fe05 drm/amdgpu: switch to amdgpu folder for firmware files v2
v2: keep using radeon folder for CIK

Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-06-03 21:03:36 -04:00
Christian König
3cb485f340 drm/amdgpu: fix context switch
Properly protect the state and also handle submission failures.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
2015-06-03 21:03:34 -04:00
Christian König
d2edb07b10 drm/amdgpu: cleanup HDP flush handling
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
2015-06-03 21:03:32 -04:00
Jammy Zhou
aa2bdb2476 drm/amdgpu: add CE preamble flag v3
The CE preamble IB can be dropped for the same context

v2: use the flags directly
v3: remove 'CE' for potential preamble usage by other rings

Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-06-03 21:03:31 -04:00
Jammy Zhou
de807f818b drm/amdgpu: add flags for amdgpu_ib structure
Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-06-03 21:03:30 -04:00
Jack Xiao
74a5d1656e drm/amdgpu: allow unaligned memory access (v2)
Set up the CP and SDMA for proper unaligned memory access.
Required for OpenCL 2.x

v2: udpate commit message

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-06-03 21:03:28 -04:00
Alex Deucher
aaa36a976b drm/amdgpu: Add initial VI support
This adds initial support for VI asics.  This
includes Iceland, Tonga, and Carrizo.  Our inital
focus as been Carrizo, so there are still gaps in
support for Tonga and Iceland, notably power
management.

Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03 21:03:17 -04:00