Remove platform device instantiating of the audio, which results in
board-t5325.c being removed. A DT node will be added to take its
place.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1399141819-23924-7-git-send-email-andrew@lunn.ch
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The initial release of the Armada 375 DB board has an Armada 375
Z1 stepping silicon. This commit introduces a quirk that allows
to workaround a series of issues with the thermal sensor in this
stepping, but updating the devicetree:
* Updates the compatible string for the thermal, so the driver
can perform a specific initialization of the sensor.
* Moves the offset of the thermal control register. This quirk
allows to specifiy the correct (A0 stepping) offset in the
devicetree.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1398371004-15807-9-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The name of the two parameters of mvebu_get_soc_id were inverted. This
patch fix it in order to have a more readable code.
Reported-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397925170-8202-3-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
l2x0_of_init function is always defined
arch/arm/include/asm/hardware/cache-l2x0.h: in case of
CONFIG_CACHE_L2X0 is not selected then a placeholder is defined.
Then there is no need to have ifdef around l2x0_of_init.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397925170-8202-2-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In order to have well encapsulated code, we use notifier callbacks for
CPU_PM_ENTER and CPU_PM_EXIT inside the mvebu power management code.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-10-git-send-email-gregory.clement@free-electrons.com
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Following the integration into mach-mvebu of the Kirkwood ARMv5
support, we need to be more careful about which files get built. For
example, the pmsu.c file now calls wfi(), which only exists on ARMv7
platforms.
Therefore, this commit changes mach-mvebu/Makefile to build the Armada
370/XP/375/38x specific files only when CONFIG_MACH_MVEBU_V7 is
enabled.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1398709239-6126-1-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The cpu idle support will need to access to Power Management Service
Unit. This commit adds the architecture related functions that will be
used in the idle path of the cpuidle driver.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-9-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds a function which adjusts the PMSU configuration to
automatically power down the L2 and coherency fabric when we enter a
certain idle state.
This feature is part of the Power Management Service Unit of the
Armada 370 and Armada XP SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-8-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
When going to deep idle we need to disable the SoC snooping (aka
hardware coherency support). Playing with the coherency fabric
requires to use assembly code to be sure that the compiler doesn't
reorder the instructions nor do wrong optimization.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-7-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Actually enabling coherency and adding a CPU on a SMP group are two
different operations which can be done separately. This patch splits
this in two functions.
Moreover as they use common pattern, this patch also creates local low
level functions (ll_get_coherency_base and ll_get_cpuid) to be used by
the exposed functions (ll_add_cpu_to_smp_group and
ll_enable_coherency)
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-6-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
set_cpu_coherent() took the SMP group ID as parameter. But this
parameter was never used, and the CPU always uses the SMP group 0. So
we can remove this parameter.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-5-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
ll_set_cpu_coherent is always used on the current CPU, so instead of
passing the CPU id as argument, ll_set_cpu_coherent() can find it by
itself.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-4-git-send-email-gregory.clement@free-electrons.com
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In order to be able to deal with the MMU enabled and the MMU disabled
cases, the base address of the coherency registers was passed to the
function. The address by itself was not interesting as it can't change
for a given SoC, the only thing we need is to have a distinction
between the physical or the virtual address.
This patch add a check of the MMU bit to choose the accurate address,
then the calling function doesn't have to pass this information.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-3-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Since the Armada 38x PMSU registers are slightly different than the
Armada 370/XP PMSU ones, we introduce a new compatible string
"armada-380-pmsu" in the PMSU driver. These differences are not
visible for the current usage of the PMSU, but they might become
visible in the future.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-8-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Due to internal bootrom issue, CPU[1] initial jump code (four
instructions) should be placed in SRAM memory of the SoC. In order to
achieve this, we have to unmap the BootROM and at some specific
location where the BootROM was place, create a specific MBus window
for the SRAM. This SRAM is initialized with a few instructions of code
that allows to jump into the real secondary CPU boot address.
This workaround will most likely be disabled when newer steppings of
the Armada 375 will be made available, in which case a dynamic test
based on mvebu-soc-id will be added.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-10-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-10-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds the SMP support for Armada 375 and Armada 38x. It
turns out that the SMP logic for both of these SOCs are fairly
similar, the only differences being:
* A different method to set the secondary CPU boot address
* An Armada 375 specific workaround needed for the early Z1 stepping,
added by the following patch.
Other than that, the patch is fairly straightforward and adds the
usual platsmp and headsmp code, defining the smp_operations structure
that is referenced from the DT_MACHINE structures.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-9-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-9-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In order to boot the secondary CPUs on Armada 375, we need to set the
boot address of these CPUs, through a register part of the System
Controller (this deviates from the Armada XP design, where the boot
address was defined using a register part of the PMSU unit).
Therefore, this commit adds a new helper function in the System
Controller driver to set the secondary CPU boot address.
Moreover, it moves the System Controller initialization as an
early_initcall(), since arch_initcall() is too late for an SMP-related
initialization.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds the CPU_METHOD_OF_DECLARE declaration for the Armada
XP SMP operations. Note that the .smp_ops field of Armada XP
DT_MACHINE structure is kept, in order to ensure we remain compatible
with older Device Trees that do not include the "enable-method"
property for the CPUs.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The pmsu.c driver contained an armada_xp_boot_cpu() function that sets
the boot address of a secondary CPUs and deasserts the reset. However,
the Armada 375 needs a slightly different logic, so it makes more
sense to move this code into the Armada XP specific platsmp.c.
In order to achieve this, the mvebu_pmsu_set_cpu_boot_addr() function
is exported. It will be needed for both the Armada XP and Armada 38x
SMP implementations.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Some irqchip initialization must be done on secondary CPUs. On mvebu
platforms, this is currently achieved by having the
arch/arm/mach-mvebu/platsmp.c code directly call into a function
exported by the irqchip driver, which isn't really nice.
This commit changes this by using the same solution as the one used in
the GIC driver: the irqchip driver registers a CPU notifier, which is
used to do the secondary CPU IRQ initialization. This way, the irqchip
driver is completely autonomous, and the function no longer needs to
be exposed from the irqchip driver to the SoC code.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-6-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Instead of having the SoC code in arch/arm/mach-mvebu/platsmp.c do the
set_smp_cross_call() to register the IPI-triggering function, it makes
more sense to do exactly what the GIC driver is doing: let the irqchip
driver do it. This way, it avoids having to expose the
armada_mpic_send_doorbell() function between the irqchip driver and
the SoC code.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The tsadcc node is useless as it doesn't refer to anything and the touchscreen
is handled by the adc0 node.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Rodolfo Giometti <giometti@linux.it>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
atmel_tsadcc has been removed, stop selecting it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
atmel_tsadcc is not allowing to use the remaining ADC channels while at91_adc
does. Completely switch to at91_adc and remove the tsadcc platform_data for
at91sam9rl and at91sam9rl based boards.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
atmel_tsadcc is not allowing to use the remaining ADC channels while at91_adc
does. Completely switch to at91_adc and remove the tsadcc platform_data for
at91sam9g45 and at91sam9g45 based boards.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
at91_adc now supports reading a touchscreen for ADCs without a TSMR register.
Enable touchscreen support through at91_adc. This allows to use both a
touchscreen and the remaining ADC channel at the same time.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The ADC clock needs to be defined to enable the at91_adc driver. It is defined
to the same speed that is used for atmel_tsadcc.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
That include file is now only used by the at91_adc driver, remove it from
include/mach for better driver separation.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
at91_adc now supports reading a touchscreen for ADCs without a TSMR register.
Enable touchscreen support through at91_adc. This allows to use both a
touchscreen and the remaining ADC channel at the same time.
Also, lower the clock for the ADC as it allows to have more stable reads and
this is the speed used by atmel_tsadcc.
It lowers the maximum throughput rate from 440000 samples per second to 12958
samples per second. It shouldn't be an issue as the CPU is not able to keep up
reading samples at that frequency.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Old ADCs, as present on the sam9rl and the sam9g45 don't have a TSMR register
and the touchscreen support should be handled differently.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
num_channels and registers are not used anymore since they are defined inside
the at91_adc driver and assigned by matching the id_table.
Also, remove the mach/at91_adc.h include that is not necessary anymore.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
num_channels and registers are not used anymore since they are defined inside
the at91_adc driver and assigned by matching the id_table.
Also, remove the mach/at91_adc.h include that is not necessary anymore.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Move at91sam9rl SoC to the new main/slow clock model.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define crystal properties of sama5d3 xplained board.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define crystal frequencies of sama5d3xcm boards.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Replace the old main and clk definitions (fixed rate clk) by the new main and
slow clk subtree definition (ck = mux(rc_osc, osc)).
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This moves the <mach/gpio.h> header in the AT91 platform down
into the machine directory and removes the reliance on
MACH_NEED_GPIO_H from the AT91.
This does not move the platform to GENERIC_GPIO but localize
the remaining work to be done for this to the mach-at91
folder.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
[nicolas.ferre@atmel.com: adapt to newer kernel, add rsi-ews board]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The boot ROM on Tegra SoCs supports booting into forced recovery mode
(RCM) by setting a bit in the PMC scratch register 0. Similarily, the
Android bootloader examines some of the bits in this register to disable
autoboot or enter recovery mode.
Support these modes by setting the corresponding bits depending on the
specified reboot command (forced-recovery, bootloader, recovery). Recent
systemd-based distributions allow this to be specified using an optional
argument to the reboot command.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable CPUidle so it's easier for maintainers to notice
if some future code changes cause regressions.
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
On N900 there are nice LEDs that show the state of the
sys_clkreq and sys_off_mode pins.
These LEDs go low when the system enters deeper idle
states. The left LED shows the state of the sys_clkreq
pin, and goes off during retention idle. The right LED
shows the state of sys_off_mode pin and both go off
during off idle.
As N900 is a battery operated device, these LEDs should
be off most of the time. So let's enable them by default
so we can make sure the system is mostly idle.
This allows the maintainers to also immediately test
patches for PM regressions by looking at the LEDs,
which certainly makes my life easier.
The LED can naturally be disabled during runtime with:
# echo none > /sys/class/leds/debug::sleep/trigger
Note that we don't currently have support for omap3
errata 1.158 that remuxes GPIO pins to INPUT_PULLUP |
MUX_MODE7 for the duration of idle. This means that the
GPIO pins set high will go down during off idle. In this
case it does not matter as the sys_off_mode goes down
too, but there's still a slim chance of false off idle
LED signals. If in doubt, false LED signals can be
verified by the sys_off_mode or vdd_core values.
Also note that to allow the UARTs to autoidle, the
following needs to be run on N900 to enable off idle:
#!/bin/sh
uarts=$(find /sys/class/tty/ttyO*/device/power/ -type d)
for uart in $uarts; do
echo 3000 > $uart/autosuspend_delay_ms
done
uarts=$(find /sys/class/tty/ttyO*/power/ -type d)
for uart in $uarts; do
echo enabled > $uart/wakeup
echo auto > $uart/control
done
echo 1 > /sys/kernel/debug/pm_debug/enable_off_mode
For retention idle, change the above to set 0 to
enable_off_mode.
Also note that without the twl4030 PM scripts the actual
voltage scaling won't happen for off idle so we only get
voltage scaling over I2C4 for retention idle. I'll do
some device tree patches for those also a bit later on.
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Pali Rohár <pali.rohar@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Sebastian Reichel <sre@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Acked-by: Aaro Koskinen <aaro.koskinen@iki.fi>
[tony@atomide.com: also make sure the LEDs get built to see PM regressions]
Signed-off-by: Tony Lindgren <tony@atomide.com>
We are currently disabling the init of voltage scaling
for device tree. With the voltage scaling problems fixed
for omap3 in general, there's no need to disable the voltage
scaling init for device tree based booting.
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Almost certainly any sane board has the twl4030 has the I2C4
pins connected as those are needed for voltage control during
idle. If the I2C4 lines are not properly muxed, any voltage
scaling over I2C4 will fail.
Let's mux those pins by default, the boards that are not using
them can still configure things separately.
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Currently we're attempting to use a static value for the
voltctrl register that only works for controlling the PMIC
over I2C4. For using sys_off_mode signaling, we need to update
update clksetup, voltsetup1, voltsetup2 and voltctrl registers
dynamically depending on the idle state.
So let's fix this by configuring things for I2C4 controlled idle
and sys_off_mode pin controlled idle, and then write the
configured register values depending on the idle state. This
is similar what N900 kernel is doing too.
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit c589eb3869 (ARM: OMAP3: VC: calculate ramp times)
started using regulator slew rates for calculating the idle
mode start-up times. This works fine for I2C4 controlled
regulator scaling as the regulators are never completely
turned off.
For sys_off_mode pin controlled PMIC scripts, the slew rate
based calculations won't work at all as the regulators are
completely turned off and the start-up time is much longer.
This means currently omap3_set_off_timings currently has
zero chance of working on any real hardare. The current code
is broken in at least the following ways:
1. It attempts to use the default ULONG_MAX value for the
oscillator start-up value as we're currently never
initializing the start-up value.
2. It relies on a magic number potentially set by the
bootloader for volsetup2 register.
3. If no magic value is passed, it attempts to calculate
voltsetup2 register based on the regulator slew rate.
This won't work as there is roughly at least five
times the delay needed for turning on vdd1 and vdd2
regulators.
4. It does duplicate register write to OMAP3_PRM_VOLTOFFSET
5. It duplicates the code for omap_usec_to_32k unnecessarily
6. It initialized global registers twice, once for each channel
Let's just remove the broken code and call omap3_set_i2c_timings
directly, we're better off with this function doing nothing until
it's fixed. And otherwise further fixes to omap3_set_off_timings
will be unreadable.
And let's get rid of omap3_set_clksetup as that's not needed
for off-idle controlled by I2C4 as in that case the oscillator
is never shut down.
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
While debugging legacy mode vs device tree booted PM regressions,
I noticed that omap3 is not toggling sys_clkreq and sys_off_mode
pins like it should.
The sys_clkreq and sys_off_mode pins are not toggling because of
the following issues:
1. The default polarity for the sys_off_mode pin is wrong.
OFFMODE_POL needs to be cleared for sys_off_mode to go down when
hitting off-idle, while CLKREQ_POL needs to be set so sys_clkreq
goes down when hitting retention.
2. The values for voltctrl register need to be updated dynamically.
We need to set either the retention idle bits, or off idle bits
in the voltctrl register depending the idle mode we're targeting
to hit.
Let's fix these two issues as otherwise the system will just
hang if any twl4030 PMIC idle scripts are loaded. The only case
where the system does not hang is if only retention idle over I2C4
is configured by the bootloader.
Note that even without the twl4030 PMIC scripts, these fixes will
do the proper signaling of sys_clkreq and sys_off_mode pins, so
the fixes are needed to fix monitoring of PM states with LEDs or
an oscilloscope.
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We've had deeper idle states working on omaps for few years now,
but only in the legacy mode. When booted with device tree, the
wake-up events did not have a chance to work until commit
3e6cee1786 (pinctrl: single: Add support for wake-up interrupts)
that recently got merged. In addition to that we also needed commit
79d9701559 (of/irq: create interrupts-extended property) and
9ec36cafe4 (of/irq: do irq resolution in platform_get_irq) that
are now also merged.
So let's fix the wake-up events for some selected omaps so devices
booted in device tree mode won't just hang if deeper power states
are enabled, and so systems can wake up from suspend to the serial
port event.
Note that there's no longer need to specify the wake-up bit in
the pinctrl settings, the request_irq on the wake-up pin takes
care of that.
Cc: devicetree@vger.kernel.org
Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
[tony@atomide.com: updated comments, added board LDP]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Power management code which is only used by
sh7372 (SH-Mobile AP4) based Mackerl board
* Ignore callbacks for subsys generic_pm_domain_data
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Merge tag 'renesas-soc2-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Merge "Second Round of Renesas ARM Based SoC Updates for v3.16" from Simon
Horman:
Power management code which is only used by
sh7372 (SH-Mobile AP4) based Mackerl board
* Ignore callbacks for subsys generic_pm_domain_data
* tag 'renesas-soc2-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Ignore callbacks for subsys generic_pm_domain_data
Signed-off-by: Olof Johansson <olof@lixom.net>
This will allow to better isolate various options, and reduce the overall
kernel size if we're interested in only one of the SoCs.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
the merge window.
- A fix from Oleg to async page faults.
- A bunch of small ARM changes.
- A trivial patch to use the new MSI-X API introduced during the merge
window.
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM fixes from Paolo Bonzini:
- Fix for a Haswell regression in nested virtualization, introduced
during the merge window.
- A fix from Oleg to async page faults.
- A bunch of small ARM changes.
- A trivial patch to use the new MSI-X API introduced during the merge
window.
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM: ARM: vgic: Fix the overlap check action about setting the GICD & GICC base address.
KVM: arm/arm64: vgic: fix GICD_ICFGR register accesses
KVM: async_pf: mm->mm_users can not pin apf->mm
KVM: ARM: vgic: Fix sgi dispatch problem
MAINTAINERS: co-maintainance of KVM/{arm,arm64}
arm: KVM: fix possible misalignment of PGDs and bounce page
KVM: x86: Check for host supported fields in shadow vmcs
kvm: Use pci_enable_msix_exact() instead of pci_enable_msix()
ARM: KVM: disable KVM in Kconfig on big-endian systems
The DRM_PANEL_SIMPLE is needed by the eukrea
mbimxsd51's displays.
Signed-off-by: Denis Carikli <denis@eukrea.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Let CONFIG_CRYPTO_DEV_MXS_DCP driver to be built by default.
Generated by doing:
make mxs_defconfig
Manually selected the CONFIG_CRYPTO_DEV_MXS_DCP driver
make savedefconfig
cp defconfig arch/arm/configs/mxs_defconfig
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The device tree version for the babbage board (imx51-babbage.dtb) has a more
complete support than the board file version, so remove the board file source
code.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
CODA7 clock lookups are now defined in the device tree.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
- Remove unused <asm/mach/time.h> inclusion.
- Use predefined constant for CS8900A base address.
- Use DEFINE_RES_MEM() macro for NOR flash resource.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Instead of using init() and exit() hooks from framebuffer driver
to control power of LCD, introduce fixed voltage regulator for
this purpose.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add choice for low-level debug UART. Similar to i.MX6, there is a
numeric configuration, valid choices are 0 to 3.
Note that the kernel assumes that the boot loader initialized clock
properly.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch replaces direct handling of peripheral bits with GPIOs by
using basic-mmio-gpio driver. As a result this change eliminate some
low-level code and removes custom io_map() from the board.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This branch contains a pair of important bug fixes for the DT code:
- Fix some incorrect binding property names before they enter common usage
- Fix bug where some platform devices will be unable to get their
interrupt number when they depend on an interrupt controller that is
not available at device creation time. This is a problem causing
mainline to fail on a number of ARM platforms.
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Merge tag 'dt-for-linus' of git://git.secretlab.ca/git/linux
Pull devicetree bug fixes from Grant Likely:
"These are some important bug fixes that need to get into v3.15.
This branch contains a pair of important bug fixes for the DT code:
- Fix some incorrect binding property names before they enter common
usage
- Fix bug where some platform devices will be unable to get their
interrupt number when they depend on an interrupt controller that
is not available at device creation time. This is a problem
causing mainline to fail on a number of ARM platforms"
* tag 'dt-for-linus' of git://git.secretlab.ca/git/linux:
of/irq: do irq resolution in platform_get_irq
of: selftest: add deferred probe interrupt test
dt: Fix binding typos in clock-names and interrupt-names
Enable PWM drivers and the PWM-based backlight driver.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
The kvm/mmu code shared by arm and arm64 uses kalloc() to allocate
a bounce page (if hypervisor init code crosses page boundary) and
hypervisor PGDs. The problem is that kalloc() does not guarantee
the proper alignment. In the case of the bounce page, the page sized
buffer allocated may also cross a page boundary negating the purpose
and leading to a hang during kvm initialization. Likewise the PGDs
allocated may not meet the minimum alignment requirements of the
underlying MMU. This patch uses __get_free_page() to guarantee the
worst case alignment needs of the bounce page and PGDs on both arm
and arm64.
Cc: <stable@vger.kernel.org> # 3.10+
Signed-off-by: Mark Salter <msalter@redhat.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
This merges the patch to fix possible loss of dirty bit on munmap() or
madvice(DONTNEED). If there are concurrent writers on other CPU's that
have the unmapped/unneeded page in their TLBs, their writes to the page
could possibly get lost if a third CPU raced with the TLB flush and did
a page_mkclean() before the page was fully written.
Admittedly, if you unmap() or madvice(DONTNEED) an area _while_ another
thread is still busy writing to it, you deserve all the lost writes you
could get. But we kernel people hold ourselves to higher quality
standards than "crazy people deserve to lose", because, well, we've seen
people do all kinds of crazy things.
So let's get it right, just because we can, and we don't have to worry
about it.
* safe-dirty-tlb-flush:
mm: split 'tlb_flush_mmu()' into tlb flushing and memory freeing parts
Pull arm fixes from Russell King:
"A number of fixes for the PJ4/iwmmxt changes which arm-soc forced me
to take during the merge window. This stuff should have been better
tested and sorted out *before* the merge window"
* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: 8042/1: iwmmxt: allow to build iWMMXt on Marvell PJ4B
ARM: 8041/1: pj4: fix cpu_is_pj4 check
ARM: 8040/1: pj4: properly detect existence of iWMMXt coprocessor
ARM: 8039/1: pj4: enable iWMMXt only if CONFIG_IWMMXT is set
ARM: 8038/1: iwmmxt: explicitly check for supported architectures
Here are some small staging and IIO driver fixes for 3.15-rc3.
Nothing major at all, just some assorted issues that people have reported.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'staging-3.15-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
Pull staging / IIO driver fixes from Greg KH:
"Here are some small staging and IIO driver fixes for 3.15-rc3.
Nothing major at all, just some assorted issues that people have
reported"
* tag 'staging-3.15-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging:
staging: comedi: usbdux: bug fix for accessing 'ao_chanlist' in private data
iio: adc: mxs-lradc: fix warning when buidling on avr32
iio: cm36651: Fix i2c client leak and possible NULL pointer dereference
iio: querying buffer scan_mask should return 0/1
staging:iio:ad2s1200 fix a missing break
iio: adc: at91_adc: correct default shtim value
ARM: at91: at91sam9260: change at91_adc name
ARM: at91: at91sam9g45: change at91_adc name
iio: cm32181: Fix read integration time function
iio: adc: at91_adc: Repair broken platform_data support
Following the move to pure DT-based probing of the GPIO controllers on
Orion5x, some code in plat-orion/orion-gpio.c can be removed as it is
no longer used.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-39-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Following the move of the Orion5x Device Tree support to use
irqchip_init() for the interrupt controller probing, the
plat-orion/irq.c code for DT-probing of the interrupt controller is no
longer necessary, so we can get rid of it.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-38-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit converts the Maxtor Shared Storage II Orion5x platform to
the Device Tree. The only remaining things not converted are PCI and
the special power off method.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-37-git-send-email-thomas.petazzoni@free-electrons.com
Cc: Sylver Bruneau <sylver.bruneau@googlemail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit converts the LaCie d2 Network platform to the Device Tree.
All devices except LEDs are converted, because the LED code needs a
non-LED GPIO to be set to a given value for the LEDs to work, and this
cannot yet be easily represented in DT.
Also, references to the LaCie Big Disk Network platform are lost,
because this platform apparently has exactly the same hardware support
as the LaCie d2 Network, so their Device Tree files would be
identical.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-36-git-send-email-thomas.petazzoni@free-electrons.com
Cc: Simon Guinot <sguinot@lacie.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit converts the RD-88F5182 platform to the Device Tree. All
devices except the PCI are converted to the Device Tree.
It is worth noting that:
* The PCI description for the DT case is kept in board-rd88f5182.c.
* The existing non-DT support in rd88f5182-setup.c is kept as is, in
order to allow testing of a given platform in both DT and non-DT
cases. It will ultimately be removed, once we no longer care about
non-DT support for Orion5x.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-35-git-send-email-thomas.petazzoni@free-electrons.com
Cc: Ronen Shitrit <rshitrit@marvell.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The edmini_v2 platform is now fully converted to the Device Tree, so
we can get rid of the old style board-file and the related Kconfig
option.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1398202002-28530-34-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In preparation to the complete removal of non-DT support for
edmini_v2, this commit copies the TODO list of things to support from
the old-style board file into the Device Tree of edmini_v2.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-33-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit converts the already partially DT-converted edmini_v2
platform to use the Device Tree for NOR flash, using the Device Bus.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-32-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit converts the already partially DT-converted edmini_v2
platform to use the Device Tree for USB.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-31-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit converts the already partially DT-converted edmini_v2
platform to use the Device Tree for I2C bus and devices.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-30-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit converts the already partially DT-converted edmini_v2
platform to use the Device Tree for pinctrl.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-29-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Several platforms will most likely use similar pinctrl configurations
for SATA0 and SATA1, so we declare those common configurations in the
Orion5x DT file.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1398202002-28530-28-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds the necessary SoC-level Device Tree definitions to
describe the Device Bus of Orion5x SOCs. The Device Bus is mainly used
to connect NOR flashes to the system.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1398202002-28530-27-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit fixes the Orion5x SoC definition to:
* Not define a clock-frequency, as it should be described on a
per-board basis.
* Declare the appropriate clock reference, so that the driver can do
correct divisors calculations for the I2C bus.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1398202002-28530-26-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit declares the pinctrl device in the Orion5x 5182 Device
Tree files, and ensures that the Orion pinctrl driver is compiled.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1398202002-28530-25-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit switches the Orion5x platforms described through DT to use
a DT-defined interrupt controller and timer.
This involves:
* Describing in the DT the bridge interrupt controller, which is a
child interrupt controller to the main one, which is used for timer
and watchdog interrupts.
* Describing in the DT the timer.
* Adding in the DT the interrupt specifications for the watchdog.
* Selecting the ORION_IRQCHIP and ORION_TIMER drivers to be compiled.
* Change board-dt.c to no longer have an ->init_time() callback,
since the default callback will work fine: it calls
clocksource_of_init() and of_clk_init(), as needed.
* Implement a multi-IRQ handler for non-DT platforms in
mach-orion5x/irq.c.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-24-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Moving to the Device Tree implies having CONFIG_MULTI_IRQ_HANDLER
enabled, even for non-DT platforms (if we want both DT and non-DT
platforms to be supported in a single kernel).
However, the common CONFIG_MULTI_IRQ_HANDLER handler for non-DT
platforms in plat-orion/irq.c doesn't match the needs of
Orion5x. Also, it doesn't make much sense for orion_irq_init() to
register the multi-IRQ handler: orion_irq_init() is called once for
each IRQ cause/mask tuple, while the multi-IRQ handler only needs to
be registered once.
To solve this problem, we move the multi-IRQ handle in per-platform
code: mach-kirkwood/irq.c and mach-dove/irq.c. The Orion5x variant
will be introduced in a followup commit. Of course, this code will
ultimately be completely removed once all boards are converted to the
Device Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-23-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Until the previous commit, the Orion5x clocks were not described in
the Device Tree. Now that they are described in the Device Tree, we
can replace the manual 'clock-frequency' property in the UART nodes
by a nicer 'clocks' reference in those UART nodes.
This commit consequently removes the 'clock-frequency' property from
the LaCie edmini_v2 board, which is at this point the only Orion5x
board converted to the Device Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-22-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit moves the Orion5x platforms using the Device Tree to use
the recently introduced clock driver for Orion5x. To achieve that, it:
* Adds the necessary DT description of the clock.
* Selects ORION_CLK to enable the compilation of the clock driver.
* Call of_clk_init() instead of the Orion5x-specific clock
initialization function.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1398202002-28530-21-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit renames the XOR engine Device Tree node to
dma-controller@, to conform with the standard node name proposed by
the ePAPR.
Suggested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-19-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit converts the existing devices described in the edmini_v2
Device Tree to use node labels: the UART and SATA device. Also, it
reorders the eth and mdio node label references to be sorted
alphabetically.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-18-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds the new linux,stdout-path to the edmini_v2 platform,
pointing to the serial device use for the console.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-17-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
As noted by Sebastian Hesselbarth, the Device Tree nodes for GPIO keys
and LEDs should be named gpio-keys and gpio-leds.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-16-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In order to ease identification of devices, it is useful to have
Device Tree labels on all devices. This commit adds such labels to the
Orion5x SoC Device Tree file.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-15-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit switches the Orion5x Device Tree files to use the DT
representation and probing for the mvebu-mbus driver. The changes are
mainly:
* Re-organize the DT to follow the same organization as the one used
on Armada 370/XP, which is needed for mvebu-mbus to work: a
top-level soc { ... } node, which corresponds to the MBus bus, and
a sub-node internal-regs { ... } for all peripherals whose register
sit only in the "Internal Register Window". This change re-indents
by one level the definition of all nodes in the Device Tree, which
explains the large change.
* Use custom functions orion5x_dt_init_early() and
orion5x_dt_init_time() instead of orion5x_init_early() and
orion5x_timer_init() as we now want the MBus driver to be probed
from the Device Tree. We still use the old-style timer
initialization, but that will be changed in a followup commit.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398202002-28530-14-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The orion5x-lacie-ethernet-disk-mini-v2.dts can benefit from using
gpio.h and input.h dt-bindings headers to replace hardcoded values by
more meaningful macros.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1398202002-28530-13-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit switches the Orion5x Device Tree files to use C
preprocessor based includes, as it will allow us to use definitions
from header files in future commits.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1398202002-28530-12-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The interrupt controller node was located outside of the ocp@f1000000
node, which doesn't make much sense: like any other device, the
interrupt controller has registers located in the "Internal Registers
Window", so it is much more logical to have it under the ocp@f1000000
node.
It is even more important as we are going to move Orion5x to use the
Device Tree binding of the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1398202002-28530-11-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
KVM currently crashes and burns on big-endian hosts, so don't allow it
to be selected until we've got that fixed.
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
The mmu-gather operation 'tlb_flush_mmu()' has done two things: the
actual tlb flush operation, and the batched freeing of the pages that
the TLB entries pointed at.
This splits the operation into separate phases, so that the forced
batched flushing done by zap_pte_range() can now do the actual TLB flush
while still holding the page table lock, but delay the batched freeing
of all the pages to after the lock has been dropped.
This in turn allows us to avoid a race condition between
set_page_dirty() (as called by zap_pte_range() when it finds a dirty
shared memory pte) and page_mkclean(): because we now flush all the
dirty page data from the TLB's while holding the pte lock,
page_mkclean() will be held up walking the (recently cleaned) page
tables until after the TLB entries have been flushed from all CPU's.
Reported-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Tested-by: Dave Hansen <dave.hansen@intel.com>
Acked-by: Hugh Dickins <hughd@google.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: Tony Luck <tony.luck@intel.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Since we didn't get around to collect fixes in time for -rc2 over
the easter vacation, this one is unfortunately a bit larger than
we'd like for an -rc3 merge. A large set of the changes is in the
device tree sources, so I'm splitting out the description between
code changes and DT changes. Aside from omap and versatile express,
the actual code bugs are sporadic and trivial. Here is an overview:
imx:
- fix video clock settings
- fix one clock refcounting bug
omap:
- update defconfig for renamed USB PHY driver
- fix error handling in gpmc
- fix N900 video initialization regression
- fix reression in hwmod code from missing braces
- fix am43xx and omap3 clocks
- remove bogus write to voltage control register
pxa:
- fix build regression from 3.13 header cleanup
rockchip:
- fix a misleading printk string
shmobile:
- fix incorrect sound setting on multiple machines
spear:
- remove incorrect __init section annotation
tegra:
- remove a stale Kconfig entry
u300:
- update defconfig
ux500:
- enable common wireless and sensor drivers in defconfig
- more defconfig updates
vexpress:
- fix voltage calculation for opp
- fix reboot hang and warning
- fix out-of-bounds array access
- improve error handling in clock driver
overall:
- always select CLKSRC_OF in multiplatform builds
And these are the devicetree related changes:
imx:
- add missing #clock-cell properties
- fix pinctrl setting in imx6sl-evk
- fix video endpoint on imx53
- remove obsolete lvds-channel nodes (multiple patches)
- add missing second stmpe node
- fix usb host mode on dmo-edmqmx6 (multiple patches)
- fix gic node #address-cells to match usage
- add missing legacy IRQ map for PCIe
- fix microsom pincontrol setting for rgmii
- fix fatal typo in touchscreen DT usage for mx5
- list all RAM present on m53evk and mx53qsb
omap:
- fix bug in DT handling of gpmc external bus
- add DT for older revision of beagleboard
- fix regression after DT node name fixes
- remove obsolete properties for gpmc
- fix pinmux comment to match DT it refers to
- fix newly added dra7xx clock node data
- add missing clock for USB PHY
mvebu:
- add missing clock for mdio node
- fix nonstandard vendor prefixes on i2c nodes
rockchip:
- fix pin control setting for uart
shmobile:
- fix typo in DT data for pin control (multiple patches)
- fix gic node #address-cells to match usage
tegra:
- fix clock and uart DT representation to match hardware
zynq:
- add DT nodes for newly added driver
- add DT properties required for cpufreq-ondemand
overall:
- restore alphabetic order in Makefile
- grammar fixes in bindings
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Merge tag 'fixes-3.15-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Arnd Bergmann:
"Since we didn't get around to collect fixes in time for -rc2 over the
easter vacation, this one is unfortunately a bit larger than we'd like
for an -rc3 merge.
A large set of the changes is in the device tree sources, so I'm
splitting out the description between code changes and DT changes.
Aside from omap and versatile express, the actual code bugs are and
trivial. Here is an overview:
imx:
- fix video clock settings
- fix one clock refcounting bug
omap:
- update defconfig for renamed USB PHY driver
- fix error handling in gpmc
- fix N900 video initialization regression
- fix reression in hwmod code from missing braces
- fix am43xx and omap3 clocks
- remove bogus write to voltage control register
pxa:
- fix build regression from 3.13 header cleanup
rockchip:
- fix a misleading printk string
shmobile:
- fix incorrect sound setting on multiple machines
spear:
- remove incorrect __init section annotation
tegra:
- remove a stale Kconfig entry
u300:
- update defconfig
ux500:
- enable common wireless and sensor drivers in defconfig
- more defconfig updates
vexpress:
- fix voltage calculation for opp
- fix reboot hang and warning
- fix out-of-bounds array access
- improve error handling in clock driver
overall:
- always select CLKSRC_OF in multiplatform builds
And these are the devicetree related changes:
imx:
- add missing #clock-cell properties
- fix pinctrl setting in imx6sl-evk
- fix video endpoint on imx53
- remove obsolete lvds-channel nodes (multiple patches)
- add missing second stmpe node
- fix usb host mode on dmo-edmqmx6 (multiple patches)
- fix gic node #address-cells to match usage
- add missing legacy IRQ map for PCIe
- fix microsom pincontrol setting for rgmii
- fix fatal typo in touchscreen DT usage for mx5
- list all RAM present on m53evk and mx53qsb
omap:
- fix bug in DT handling of gpmc external bus
- add DT for older revision of beagleboard
- fix regression after DT node name fixes
- remove obsolete properties for gpmc
- fix pinmux comment to match DT it refers to
- fix newly added dra7xx clock node data
- add missing clock for USB PHY
mvebu:
- add missing clock for mdio node
- fix nonstandard vendor prefixes on i2c nodes
rockchip:
- fix pin control setting for uart
shmobile:
- fix typo in DT data for pin control (multiple patches)
- fix gic node #address-cells to match usage
tegra:
- fix clock and uart DT representation to match hardware
zynq:
- add DT nodes for newly added driver
- add DT properties required for cpufreq-ondemand
overall:
- restore alphabetic order in Makefile
- grammar fixes in bindings"
* tag 'fixes-3.15-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (66 commits)
ARM: vexpress/TC2: Convert OPP voltage to uV before storing
power/reset: vexpress: Fix restart/power off operation
dt: tegra: remove non-existent clock IDs
clk: tegra: remove non-existent clocks
ARM: tegra: remove UART5/UARTE from tegra124.dtsi
ARM: tegra: remove TEGRA_EMC_SCALING_ENABLE
ARM: Tidy up DTB Makefile entries
ARM: fix missing CLKSRC_OF on multi-platform
ARM: spear: add __init to spear_clocksource_init()
ARM: pxa: hx4700.h: include "irqs.h" for PXA_NR_BUILTIN_GPIO
arm/mach-vexpress: array accessed out of bounds
clk: vexpress: NULL dereference on error path
ARM: OMAP2+: Fix GPMC remap for devices using an offset
ARM: zynq: dt: Add I2C nodes to Zynq device tree
ARM: zynq: DT: Add 'clock-latency' property
ARM: OMAP2+: Fix oops for GPMC free
ARM: dts: Add support for the BeagleBoard xM A/B
ARM: dts: Grammar /that will/it will/
ARM: dts: Grammar /is uses/ is used/
ARM: OMAP2+: Fix config name for USB3 PHY
...
- fix for a long-standing bug in __break_lease that can cause soft lockups
- renaming of file-private locks to "open file description" locks, and the
command macros to more visually distinct names.
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Merge tag 'locks-v3.15-2' of git://git.samba.org/jlayton/linux
Pull file locking fixes from Jeff Layton:
"File locking related bugfixes for v3.15 (pile #2)
- fix for a long-standing bug in __break_lease that can cause soft
lockups
- renaming of file-private locks to "open file description" locks,
and the command macros to more visually distinct names
The fix for __break_lease is also in the pile of patches for which
Bruce sent a pull request, but I assume that your merge procedure will
handle that correctly.
For the other patches, I don't like the fact that we need to rename
this stuff at this late stage, but it should be settled now
(hopefully)"
* tag 'locks-v3.15-2' of git://git.samba.org/jlayton/linux:
locks: rename FL_FILE_PVT and IS_FILE_PVT to use "*_OFDLCK" instead
locks: rename file-private locks to "open file description locks"
locks: allow __break_lease to sleep even when break_time is 0
ARM_ERRATA_775420 needs to be enabled.
A data cache maintenance operation which aborts, followed by an ISB,
without any DSB in-between, might lead to deadlock.
Affects: bug present in Cortex-A9 r3p0 and earlier. Fixed in r4p0.
Cortex-A9 r3p0 is used in a multitude of Broadcom parts including
the bcm21664, bcm281xx, 5301x families of devices.
Signed-off-by: Scott Branden <sbranden@broadcom.com>
Tested-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
Currently, Broadcom SoC options are shown whenever ARCH_MULTIPLATFORM
is enabled. Restrict this so they are only seen when ARCH_MULTI_V6_V7
variants are enabled.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
[mporter: added commit log message]
Signed-off-by: Matt Porter <mporter@linaro.org>
These source files contain only level-2 cache initialization code,
so rename them to make that fact more obvious.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
The block of comments in bcm_kona_do_smc() are somewhat confusing.
This patch attempts to clarify what's going on.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
Move the code that implements the "smc" call into a C function that
uses inline assembly. This allows us to make that function private,
and enables us to get rid of "arch/arm/mach-bcm/bcm_kona_smc_asm.S".
Rename what had been the "buffer_addr" argument to be "buffer_phys"
so it's consistent with other usage in this file.
Since it's now easy to do, verify that r12 contains SEC_EXIT_NORMAL
upon completion of the SMC. There really isn't a good way to handle
the abnormal completion of a secure monitor request.
Since "bcm_kona_smc.h" is now only included from C files, eliminate
the #ifndef __ASSEMBLY__.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
Clean up a few header file includes, eliminating a few that are not
really needed and putting in their place some that are.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
Add a new config option ARCH_BCM_MOBILE_L2_CACHE that allows support
for level-2 cache to be enabled or disabled at build time for
BCM218XX and BCM21664 family SoCs.
Build support for SMC only if it's required (currently it's only
required for to support level 2 cache control).
If arch/arm/mach-bcm/kona.c gets compiled, ARCH_BCM_MOBILE_L2_CACHE
must have been selected, which implies CONFIG_CACHE_L2X0 is set.
There is therefore no need to check CONFIG_CACHE_L2X0 at the top
of kona_l2_cache_init(), so get rid of that check.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
There's logic in bcm_kona_smc() to ensure __bcm_kona_smc() gets
called on CPU 0; if already executing on CPU 0, that function is
called directly. The direct call is not protected from interrupts,
however, which is not safe.
Note that smp_call_function_single() is designed to handle the case
where the target cpu is the current one. It also gets a reference
to the CPU and disables IRQs across the call.
So we can simplify things and at the same time be protected against
interrupts by calling smp_call_function_single() unconditionally.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
Currently it is assumed that SEC_ROM_RET_OK is the only valid "good"
result of a secure monitor request. However the values that can be
returned by a secure monitor request are dependent on which service
id was provided.
We therefore should handle the result in a request-dependent way.
The most natural way to do that is to have the initiator of the
request--where bcm_kona_smc() is called--handle the result in a way
appropriate to the request.
An "smc" operation must be performed only on core 0, while the
request can be initiated from any core. To pass back the request
result, we add a new field to the bcm_kona_smc_data structure, and
have bcm_kona_smc() return that value rather than 0.
There's only one caller right now. Move the existing check of the
result out of __bcm_kona_smc() and into the kona_l2_cache_init()
where the SSAPI_ENABLE_L2_CACHE request is initiated.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
This patch just does some simple cleanup in "bcm_kona_smc.c":
- Get rid of the secure_bridge_data structure. Instead, just
define two globals that record the physical and virtual
addresses of the SMC arguments buffer. Use "buffer" instead
of "bounce" in their names. Drop of the erroneous __iomem
annotation for the physical address.
- Get rid of the initialized flag and just use a non-null buffer
address to indicate that.
- Get the size of the memory region when fetching the SMC
arguments buffer location from the device tree. Use it to
call ioremap() directly rather than requiring of_iomap() to
go look it up again.
- Do some additional validation on that memory region size.
- Flush caches unconditionally in __bcm_kona_smc(); nothing
supplies SSAPI_BRCM_START_VC_CORE as a service id.
- Drop a needless initialization of "rc" in __bcm_kona_smc().
It also deletes most of the content of "bcm_kona_smc.h" because it's
never actually used and is of questionable value anyway.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
Several conditions in bcm_kona_smc_init() are handled with BUG_ON().
That function is capable of returning an error, so do that instead.
Also, don't assume of_get_address() returns a valid pointer.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
The pointer used to pass parameters to an "smc" call is produced
through a call to ioremap(). As such, we should be using functions
like writel() to access it.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
Currently CONFIG_ARCH_BCM_MOBILE is used to select all (both)
Broadcom mobile SoC families. Instead, use that only as a config
menu switch, and define specific symbols like ARCH_BCM_281XX to
select a particular SoC family. If ARCH_BCM_MOBILE is selected, all
of the SoCs will be selected by default, but this way each can be
disabled individually as well.
Note that BCM281xx and BCM21664 both require the SMC and L2 cache
control code, so that code will be built based on ARCH_BCM_MOBILE.
Signed-off-by: Alex Elder <elder@linaro.org>
[mporter: added ARM: to the description]
Signed-off-by: Matt Porter <mporter@linaro.org>
Some Marvell PJ4B CPUs also implement iWMMXt extensions. With a
proper check for iWMMXt coprocessors now in place, enable it by
default on PJ4B. While at it, also allow to manually select
the corresponding Kconfig option.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Commit fdb487f5c9
("ARM: 8015/1: Add cpu_is_pj4 to distinguish PJ4 because it
has some differences with V7")
introduced a cpuid check for Marvell PJ4 processors to fix a
regression caused by adding PJ4 based Marvell Dove into
multi_v7.
Unfortunately, this check is too narrow to catch PJ4 used on
Dove itself and breaks iWMMXt support.
This patch therefore relaxes the cpuid mask to match both PJ4
and PJ4B. Also, rework the given comment about PJ4/PJ4B
modifications to be a little bit more specific about the
differences.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
commit fdb487f5c9
("ARM: 8015/1: Add cpu_is_pj4 to distinguish PJ4 because it
has some differences with V7")
introduced a fix for checking PJ4 cpuid to not use PJ4 specific
coprocessor access on non-PJ4 platforms.
Unfortunately, this in turn broke Marvell Armada 370/XP, both
comprising Marvell PJ4B CPUs without iWMMXt extension. Instead
of only checking for cpuid, which may not be sufficient to
determine iWMMXt support, the presence of iWMMXt coprocessors
can be checked by enabling and reading the Coprocessor ID
register (wCID, register 0 of CP1).
Therefore this adds an explicit check for the presence and correct
wCID value, before enabling iWMMXt capabilities. As a bonus, also
print the iWMMXt version of a detected coprocessor.
This has been tested to properly detect iWMMXt presence/absence on:
- PJ4, CPUID 0x560f5815, wCID 0x56052001: Marvell Dove, iWMMXt v2
- PJ4B, CPUID 0x561f5811: Marvell Armada 370, no iWMMXt
- PJ4B, CPUID 0x562f5841, wCID 0x56052001: Marvell Armada 1500, iWMMXt v2
- PJ4B, CPUID 0x562f5842: Marvell Armada XP, no iWMMXt
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This fixes PJ4 coprocessor init to only expose iWMMXt capabilities,
if the corresponding kernel support for iWMMXt is enabled.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
iwmmxt.S requires special treatment of coprocessor access registers
for PJ4 and XScale-based CPUs. It only checks for CPU_PJ4 and drops
down to XScale-based treatment on all other architectures.
As some PJ4B also come with iWMMXt and also need PJ4 treatment,
rework the corresponding preprocessor directives to explicitly
check for supported architectures and fail on unsupported ones.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
There are no active users of these callbacks, thus there are no benefit
of trying to invoke them.
Cc: Simon Horman <horms@verge.net.au>
Cc: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This series contains straight-forward fixes for different
Versatile Express infrastructure drivers:
- NULL pointer dereference on the error path in the clk driver
- out of boundary array access in the dcscb driver
- broken restart/power off implementation
- mis-interpreted voltage unit in the spc driver
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Merge tag 'vexpress/fixes-for-3.15' of git://git.linaro.org/people/pawel.moll/linux into fixes
ARM Versatile Express fixes for 3.15
This series contains straight-forward fixes for different
Versatile Express infrastructure drivers:
- NULL pointer dereference on the error path in the clk driver
- out of boundary array access in the dcscb driver
- broken restart/power off implementation
- mis-interpreted voltage unit in the spc driver
* tag 'vexpress/fixes-for-3.15' of git://git.linaro.org/people/pawel.moll/linux:
ARM: vexpress/TC2: Convert OPP voltage to uV before storing
power/reset: vexpress: Fix restart/power off operation
arm/mach-vexpress: array accessed out of bounds
clk: vexpress: NULL dereference on error path
Includes an update to 3.15-rc2
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
A few driver specific fixes here:
- SH HSPI was dealing with its clocks incorrectly which meant it didn't
work on some SoCs, fixing this also requires a small fix to one of
the SoC clock trees to avoid breaking existing users.
- The SiRF driver appears to have had several quality problems, it's
fairly new and not widely used so this isn't too worrying.
- A brute force fix for excessive locking in the Atmel driver, it needs
further investigation but this deals with the immediate issue.
- A build fix for the Blackfin driver.
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Merge tag 'spi-v3.15-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
"A few driver specific fixes here:
- SH HSPI was dealing with its clocks incorrectly which meant it
didn't work on some SoCs, fixing this also requires a small fix to
one of the SoC clock trees to avoid breaking existing users.
- The SiRF driver appears to have had several quality problems, it's
fairly new and not widely used so this isn't too worrying.
- A brute force fix for excessive locking in the Atmel driver, it
needs further investigation but this deals with the immediate
issue.
- A build fix for the Blackfin driver"
* tag 'spi-v3.15-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: atmel: Fix scheduling while atomic bug
spi: sh-hspi: Do not specifically request shyway_clk clock
ARM: shmobile: r8a7778: Use clks as MSTP007 parent
spi: sirf: make GPIO chipselect function work well
spi: sirf: set SPI controller in RISC IO chipselect mode
spi: sirf: correct TXFIFO empty interrupt status bit
spi: bfin5xx: fix build error
Pull dma-mapping fix from Marek Szyprowski:
"A small fix for dma-mapping subsystem for ARM"
* 'fixes_for_v3.15' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping:
arm: dma-mapping: Fix mapping size value
The SPC stores voltage in mV while the code assumes it was returning
uV. Convert the returned voltage to uV before storing. Also fix the
comment depicting voltage to uV.
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Tegra124 only has 4 UARTs. Parts of the documentation hint at a fifth
UART, but this appears to be left-over from earlier SoC documentation.
Remove the non-existent DT node for UART5.
Cc: <stable@vger.kernel.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
device tree based booting. And turns out BeagleBoard xM A/B
needs it's own minimal dts in addition to the related u-boot
changes. Also few minor documentation and typo fixes are merged
to get them out of the way.
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Merge tag 'omap-for-v3.15/fixes-v2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Fixes for omaps, mostly to fix some GPMC, DSS and USB issues for
device tree based booting. And turns out BeagleBoard xM A/B
needs it's own minimal dts in addition to the related u-boot
changes. Also few minor documentation and typo fixes are merged
to get them out of the way.
* tag 'omap-for-v3.15/fixes-v2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Fix GPMC remap for devices using an offset
ARM: OMAP2+: Fix oops for GPMC free
ARM: dts: Add support for the BeagleBoard xM A/B
ARM: dts: Grammar /that will/it will/
ARM: dts: Grammar /is uses/ is used/
ARM: OMAP2+: Fix config name for USB3 PHY
ARM: dts: am335x: update USB DT references
ARM: dts: OMAP2+: remove uses of obsolete gpmc,device-nand
ARM: AM335X: EVM: fix pinmux documentation in devicetree
ARM: OMAP2+: N900: remove omapdss init for DT boot
ARM: dts: dra7xx-clocks: Correct mcasp2_ahclkx_mux bit-shift
ARM: dts: omap5: Add clocks to USB3 PHY node
ARM: OMAP2+: hwmod: fix missing braces in _init()
ARM: AM43xx: fix dpll init in bypass mode
ARM: OMAP3: hwmod data: Correct clock domains for USB modules
ARM: OMAP3: PM: remove access to PRM_VOLTCTRL register
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Updates the Ux500 (U8500) defconfig
- Selects PARTITION_ADVANCED for Ux500 and U300
- Configure in IIO sensor drivers for the Ux500
- Configure in the CW1200 WLAN chip for the Ux500
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Merge tag 'ux500-defconfig-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into fixes
This is a patch set for some ST-Ericsson devices:
- Updates the Ux500 (U8500) defconfig
- Selects PARTITION_ADVANCED for Ux500 and U300
- Configure in IIO sensor drivers for the Ux500
- Configure in the CW1200 WLAN chip for the Ux500
* tag 'ux500-defconfig-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: configure for CW1200 WLAN chip
ARM: ux500: configure in sensors
ARM: u300: u300_defconfig: Enable PARTITION_ADVANCED
ARM: ux500: u8500_defconfig: Enable PARTITION_ADVANCED
ARM: ux500: update defconfig
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Correct renesas,groups in SDHI nodes of for r8a7790 (R-Car H2) based
Lager board.
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Merge tag 'renesas-dt5-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes
Fifth Round of Renesas ARM Based SoC DT Updates for v3.15
Correct renesas,groups in SDHI nodes of for r8a7790 (R-Car H2) based
Lager board.
* tag 'renesas-dt5-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: lager: correct renesas,gpios to renesas,groups in sd[02] pfc
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- A couple of dts changes for the fallout of imx-drm binding update
- Parent DI clocks to video PLL for better HDMI support
- PCIe interrupt mapping and GIC node fixes
- A series of edmqmx6 board fixes
- Other small and random fixes on imx5 and imx6 dts
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Merge tag 'imx-fixes-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes
The i.MX fixes for 3.15:
- A couple of dts changes for the fallout of imx-drm binding update
- Parent DI clocks to video PLL for better HDMI support
- PCIe interrupt mapping and GIC node fixes
- A series of edmqmx6 board fixes
- Other small and random fixes on imx5 and imx6 dts
* tag 'imx-fixes-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: i.MX6: ipu_di_sel clocks can set parent rates
ARM: imx6q: clk: Parent DI clocks to video PLL via di_pre_sel
ARM: dts: imx: add required #clock-cells for fixed-clock
ARM: dts: vybrid: drop address and size cells from GIC node
ARM: dts: imx6sl-evk: Add an entry for MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11
ARM: dts: imx53: fix apparent copy/paste error
ARM: dts: imx6q-gw5xxx: remove dead 'crtcs' property
ARM: dts: imx53-tx53: add IPU DI ports and endpoints
ARM: dts: imx6: edmqmx6: add second STMPE
ARM: dts: imx6: edmqmx6: USB H1 only supports host mode
ARM: dts: imx6: edmqmx6: Do not use the OTG switch as VBUS regulator
ARM: dts: imx6: edmqmx6: Fix usbotg id pin
ARM: dt: microsom: don't set bit 7 for ethernet mux settings
ARM: imx6q-clk: parent lvds_gate from lvds_sel
ARM: dts: imx: drop invalid size and address cells properties
ARM: dts: mx5: fix wrong stmpe-ts bindings
ARM: dts: imx53-m53evk: Fix memory region description
ARM: dts: imx53-qsb-common: Fix memory region description
ARM: dts: imx6: add PCIe interrupt mapping properties
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Commit a7cbe92cef ("ARM: tegra: remove tegra EMC scaling driver")
removed the only user of TEGRA_EMC_SCALING_ENABLE. Remove its Kconfig
entry too.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Few things were out of order:
- removed ARCH_BCM2835 duplicate
- shuffled ARCH_BCM_5301X, ARCH_U8500 and ARCH_U300 around so to keep the
list sorted
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Signed-by: Domenico Andreoli <domenico.andreoli@linux.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
In commit ddb902cc34 (ARM: centralize common multi-platform kconfig
options), CLKSRC_OF was removed from some platforms, but not added to
ARCH_MULTIPLATFORM. Fix this.
Reported-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
I get a build warning because spear_clocksource_init() calls
clocksource_mmio_init(), but it doesn't have an __init annotation.
Fix that.
Signed-off-by: Alex Elder <elder@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
hx4700 needs the same fix as in
9705e74671
"ARM: pxa: fix various compilation problems"
Fix build errors. Initial one is:
/linux/arch/arm/mach-pxa/include/mach/hx4700.h:18:32: error:
'PXA_NR_BUILTIN_GPIO' undeclared here (not in a function)
| #define HX4700_ASIC3_GPIO_BASE PXA_NR_BUILTIN_GPIO
Cc: stable@vger.kernel.org # v3.13+
Signed-off-by: Andrea Adami <andrea.adami@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
dcscb_allcpus_mask is an array of size 2.
The index variable cluster has to be checked against this limit
before accessing the array.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
The initial binding for PMSU was wrong, as it didn't take into account
all the registers from the PMSU and moreover it referred to the CPU
reset registers which are not part of PMSU.
The Power Management Unit Service block also controls the Coherency
Fabric subsystem. These registers are needed for the CPU idle
implementation for the Armada 370/XP, it allows to enter a deep CPU
idle state where the Coherency Fabric and the L2 cache are powered
down.
This commit adds support for a new compatible for the PMSU node which
includes the registers related to the coherency fabric. It also keeps
compatibility with the old compatible string.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483433-25836-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483433-25836-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Until now, the PMSU driver was using of_iomap() to map its registers,
but of_iomap() doesn't call request_mem_region(). This commit fixes
the memory mapping code of the PMSU to do so, which will also be
useful for a later commit since we will need to adjust the resource
base address and size for Device Tree backward compatibility.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483433-25836-4-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit changes the PMSU driver to no longer map itself the CPU
reset registers, and instead call into the CPU reset driver to
deassert the secondary CPUs for SMP booting.
In order to provide Device Tree backward compatibility, the CPU reset
driver is extended to not only support its official compatible string
"marvell,armada-370-cpu-reset", but to also look at the PMSU
compatible string "marvell,armada-370-xp-pmsu" to find the CPU reset
registers address. This allows old Device Tree to work correctly with
newer kernel versions. Therefore, the CPU reset driver implements the
following logic:
* If one of the normal compatible strings
"marvell,armada-370-cpu-reset" is found, then we map its first
memory resource as the CPU reset registers.
* Otherwise, if none of the normal compatible strings have been
found, we look for the "marvell,armada-370-xp-pmsu" compatible
string, and we map the second memory as the CPU reset registers.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483433-25836-3-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 370 and Armada XP have registers that allow to reset the
CPUs, which is particularly useful to take the secondary CPUs out of
reset in the context of the SMP support.
Unfortunately, an implementation mistake was originally made and the
support for these registers was integrated into the PMSU driver, which
is in fact completely unrelated. And it turns out that the Armada 375
has the same CPU reset registers, but does not have the PMSU
registers.
Therefore, this commit creates a small CPU reset driver. All it does
is provide a simple mvebu_cpu_reset_deassert() function that the SMP
support code can call to take secondary CPUs out of reset. As of this
commit, the driver isn't being used, it will be used through changes
in the following commits.
Note that we initially planned to use the 'reset controller'
framework, but it requires the addition of "resets" properties in the
Device Tree, which are causing too many problems if we want to keep
the Device Tree backward compatibility. Moreover, the 'reset
controller' framework is mainly useful when a device driver needs to
request a reset of its device from a separate reset controller. In our
case, the CPU reset handling and the SMP core code are both located in
arch/arm/mach-mvebu/ and are tightly linked together, so there's no
real benefit in going through a separate framework.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483433-25836-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 38x has a coherency unit that is similar to the one of the
Armada 375 SoC, except that it does not have the bug of the Armada 375
coherency unit that requires the XOR based workaround.
This commit therefore extends the Marvell EBU coherency code with a
new compatible string to support the Armada 38x coherency unit.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-9-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The early revisions of Armada 375 SOCs (Z1 stepping) have a bug in the
I/O coherency unit that prevents using the normal method for the I/O
coherency barrier. The recommended workaround is to use a XOR memset
transfer to act as the I/O coherency barrier.
This involves "borrowing" a XOR engine, which gets disabled in the
Device Tree so the normal XOR driver doesn't use it.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-8-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 375, like the Armada 370 and Armada XP, has a coherency
unit. However, unlike the coherency unit of 370/XP which does both CPU
and I/O coherency, the one on Armada 735 only does I/O
coherency. Therefore, instead of having two sets of registers (the
first one being used mainly to register each CPU in the coherency
fabric, the second one being used for the I/O coherency barrier), it
has only one set of register (for the I/O coherency barrier).
This commit adds a new "marvell,armada-375-coherency-fabric"
compatible string for this variant of the coherency fabric. The custom
DMA operations, and the way of triggering an I/O barrier is the same
as Armada 370/XP, so the code changes are minimal. However, the
set_cpu_coherent() function is not needed on Armada 375 and will not
work.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Contrary to the Armada 370 and XP that used the PJ4B Marvell cores,
the Armada 375 and Armada 38x use the ARM Cortex-A9. A consequence of
this is that the unit responsible for the coherency between CPUs is
now the ARM SCU, and not the Marvell coherency unit (which is still
present to do coherency with I/O devices).
Therefore this commit:
* Ensures that the selection of the Armada 375 or Armada 38x SoC
support enables the ARM SCU support in the kernel.
* Make sure to initialize the SCU at boot time.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-6-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In the mach-mvebu coherency code, instead of using
of_find_matching_node() and then of_match_node(), directly use the
of_find_matching_node_and_match() which does both at once.
We take this opportunity to also simplify the initialization of the
"type" variable.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Until now, the mvebu-mbus was guessing by itself whether hardware I/O
coherency was available or not by poking into the Device Tree to see
if the coherency fabric Device Tree node was present or not.
However, on some upcoming SoCs, the presence or absence of the
coherency fabric DT node isn't sufficient: in CONFIG_SMP, the
coherency can be enabled, but not in !CONFIG_SMP.
In order to clean this up, the mvebu_mbus_dt_init() function is
extended to get a boolean argument telling whether coherency is
enabled or not. Therefore, the logic to decide whether coherency is
available or not now belongs to the core SoC code instead of the
mvebu-mbus driver itself, which is much better.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit extends the coherency fabric code to provide a
coherency_available()function that the SoC code can call to be told
whether coherency support is available or not. On Armada 370/XP,
coherency support is available as soon as the relevant DT node is
present. On some upcoming SoCs, the DT node needs to be present *and*
the system running with CONFIG_SMP enabled.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The code that handles the coherency fabric of Armada 370 and Armada XP
in arch/arm/mach-mvebu/coherency.c made the assumption that there was
only one type of coherency fabric. Unfortunately, it turns out that
upcoming SoCs have a slightly different coherency unit.
In preparation to the introduction of the coherency support for more
SoCs, this commit:
* Introduces a data associated to the compatible string in the
compatible string match table, so that the code can differantiate
the variant of coherency unit being used.
* Separates the coherency unit initialization code into its own
function.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Pull ARM fixes from Russell King:
"Various fixes and post-merge window updates. Included here are:
- ensure Kconfig things which should be sorted remain sorted
- fix three big-endian bugs which crept in during the last merge
window
- add the renameat2 syscall
- fix big.LITTLE switcher initialisation checks
- fix kdump vmcore for LPAE kernels"
* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: add renameat2 syscall
ARM: keep arch/arm/Kconfig and arch/arm/mm/Kconfig select entries sorted
ARM: 8033/1: fix big endian __pv_phys_pfn_offset size related issue
ARM: 8032/1: bL_switcher: fix validation check before its activation
ARM: 8030/1: ARM : kdump : add arch_crash_save_vmcoreinfo
ARM: 8027/1: fix do_div() bug in big-endian systems
ARM: 8026/1: Fix emulation of multiply accumulate instructions
ARM: 8024/1: Keep DEBUG_UART_{PHYS,VIRT} entries sorted
At least the smc91x driver expects the device to be at 0x300
offset from bus base address. This does not work currently
for GPMC when booted in device tree mode as it attempts to
remap the the allocated GPMC partition to the address
configured by the device tree plus the device offset.
Note that this works just fine when booted with legacy mode.
Let's fix the issue by just ignoring any device specific
offset while remapping. And let's make sure the remap
address confirms to the GPMC 16MB minimum granularity
as listed in the TRM for GPMC_CONFIG7 BASEADDRESS bits.
Otherwise we can get something like this:
omap-gpmc 6e000000.gpmc: cannot remap GPMC CS 1 to 0x01000300
Cc: Pekon Gupta <pekon@ti.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
I noticed a regression where the omap sys_clkreq signal will never
trigger for omap3 when booted with device tree while it triggers
when booted in legacy mode. This means voltage scaling does not
do anything when booted with device tree.
Turns out the reason is we fail to initialize the SmartReflex
enable bit in twl4030 with the following error:
twl: not initialized
And that happens because we are wrongly tinkering with the twl4030
registers in arch/arm/mach-omap2/omap_twl.c before the driver is
initialized. Looking at the the SmartReflex bit enable code in
omap_twl.c, we need to always set it.
So let's fix the issue by always enabling the twl4030 SmartReflex
bit in the drivers/mfd/twl-core.c probe, and drop the related
code in omap_twl.c.
Note that we still have some twl4030 tinkering left in omap_twl.c
for the twl6030 case, but that's a different patch.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
68efd7d2fb("arm: dma-mapping: remove order parameter from
arm_iommu_create_mapping()") is causing kernel panic
because it wrongly sets the value of mapping->size:
Unable to handle kernel NULL pointer dereference at virtual
address 000000a0
pgd = e7a84000
[000000a0] *pgd=00000000
...
PC is at bitmap_clear+0x48/0xd0
LR is at __iommu_remove_mapping+0x130/0x164
Fix it by correcting mapping->size value.
Signed-off-by: Ritesh Harjani <ritesh.harjani@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
s/interrupts-names/interrupt-names/g
s/clocks-names/clock-names/g
Some of the binding files and device tree files get this wrong and the
kernel won't be able to pick it up. Fix them up now so that they don't
get widely used.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by : Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Grant Likely <grant.likely@linaro.org>
* Fix the platform data support for the at91 adc driver.
* A couple of related follow up patches get the support working again
for at91sam9260 and at91sam9g45 as the earlier patch results in a device
name change.
* A default timer value in the at91 adc driver was bonkers. Make it sane.
* Fix incorrect reporting of the integration time for the cm32181 light sensor
* Fix a missing break in the ad2s1200 driver which would have give a false
error return.
* Make sure buffer scan mask queries from userspace return 0/1 rather than
a fairly random value depending on their implementation of test_bit
* Fix leak of the i2c client and a null pointer dereference in the cm36651
driver.
* Fix a build warning on avr32 for the mxs-lradc (not exactly a critical
combination - but the issue was real).
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Merge tag 'iio-fixes-for-3.15a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-linus
Jonathan writes:
First found of IIO fixes for the 3.15 cycle.
* Fix the platform data support for the at91 adc driver.
* A couple of related follow up patches get the support working again
for at91sam9260 and at91sam9g45 as the earlier patch results in a device
name change.
* A default timer value in the at91 adc driver was bonkers. Make it sane.
* Fix incorrect reporting of the integration time for the cm32181 light sensor
* Fix a missing break in the ad2s1200 driver which would have give a false
error return.
* Make sure buffer scan mask queries from userspace return 0/1 rather than
a fairly random value depending on their implementation of test_bit
* Fix leak of the i2c client and a null pointer dereference in the cm36651
driver.
* Fix a build warning on avr32 for the mxs-lradc (not exactly a critical
combination - but the issue was real).
Fix e26a9e00af 'ARM: Better
virt_to_page() handling' replaced __pv_phys_offset with
__pv_phys_pfn_offset. Also note that size of __pv_phys_offset
was quad but size of __pv_phys_pfn_offset is word. Instruction
that used to update __pv_phys_offset which address is in r6
had to update low word of __pv_phys_offset so it used #LOW_OFFSET
macro for store offset. Now when size of __pv_phys_pfn_offset is
word, no difference between little endian and big endian should
exist - i.e no offset should be used when __pv_phys_pfn_offset
is stored.
Note that for little endian image proposed change is noop,
since in little endian case #LOW_OFFSET is defined 0 anyway.
Reported-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The switcher should not depend on MAX_CLUSTER to determine ifit should
be activated or not. In a multiplatform kernel binary it is possible to
have dual-cluster and quad-cluster platforms configured in. In that case
MAX_CLUSTER which is a build time limit should be 4 and that shouldn't
prevent the switcher from working if the kernel is booted on a b.L
dual-cluster system.
In bL_switcher_halve_cpus() we already have a runtime validation check
to make sure we're dealing with only two clusters, so booting on a quad
cluster system will be caught and switcher activation aborted.
However, the b.L switcher must ensure the MCPM layer is initialized on
the booted hardware before doing anything. The mcpm_is_available()
function is added to that effect.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Abhilash Kesavan <kesavan.abhilash@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
For vmcore generated by LPAE enabled kernel, user space
utility such as crash needs additional infomation to
parse.
So this patch add arch_crash_save_vmcoreinfo as what PAE enabled
i386 linux does.
Cc: <stable@vger.kernel.org>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Liu Hua <sdu.liu@huawei.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
In big-endian systems, "%1" get the most significant part of the value, cause the instruction to get the wrong result.
When viewing ftrace record in big-endian ARM systems, we found that
the timestamp errors:
swapper-0 [001] 1325.970000: 0:120:R ==> [001] 16:120:R events/1
events/1-16 [001] 1325.970000: 16:120:S ==> [001] 0:120:R swapper
swapper-0 [000] 1325.1000000: 0:120:R + [000] 15:120:R events/0
swapper-0 [000] 1325.1000000: 0:120:R ==> [000] 15:120:R events/0
swapper-0 [000] 1326.030000: 0:120:R + [000] 1150:120:R sshd
swapper-0 [000] 1326.030000: 0:120:R ==> [000] 1150:120:R sshd
When viewed ftrace records, it will call the do_div(n, base) function, which achieved arch/arm/include/asm/div64.h in. When n = 10000000, base = 1000000, in do_div(n, base) will execute "umull %Q0, %R0, %1, %Q2".
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Cc: <stable@vger.kernel.org> # 2.6.20+
Signed-off-by: Alex Wu <wuquanming@huawei.com>
Signed-off-by: Xiangyu Lu <luxiangyu@huawei.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Multi-platform support implies all these options are already selected and
individual platforms don't need to select them.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: David Brown <davidb@codeaurora.org>
Cc: linux-arm-msm@vger.kernel.org
Multi-platform support implies all these options are already selected and
individual platforms don't need to select them.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Christian Daudt <bcm@fixthebug.org>
Cc: Matt Porter <mporter@linaro.org>
Cc: bcm-kernel-feedback-list@broadcom.com
Multi-platform support implies all these options are already selected and
individual platforms don't need to select them.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
File-private locks have been merged into Linux for v3.15, and *now*
people are commenting that the name and macro definitions for the new
file-private locks suck.
...and I can't even disagree. The names and command macros do suck.
We're going to have to live with these for a long time, so it's
important that we be happy with the names before we're stuck with them.
The consensus on the lists so far is that they should be rechristened as
"open file description locks".
The name isn't a big deal for the kernel, but the command macros are not
visually distinct enough from the traditional POSIX lock macros. The
glibc and documentation folks are recommending that we change them to
look like F_OFD_{GETLK|SETLK|SETLKW}. That lessens the chance that a
programmer will typo one of the commands wrong, and also makes it easier
to spot this difference when reading code.
This patch makes the following changes that I think are necessary before
v3.15 ships:
1) rename the command macros to their new names. These end up in the uapi
headers and so are part of the external-facing API. It turns out that
glibc doesn't actually use the fcntl.h uapi header, but it's hard to
be sure that something else won't. Changing it now is safest.
2) make the the /proc/locks output display these as type "OFDLCK"
Cc: Michael Kerrisk <mtk.manpages@gmail.com>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Carlos O'Donell <carlos@redhat.com>
Cc: Stefan Metzmacher <metze@samba.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Frank Filz <ffilzlnx@mindspring.com>
Cc: Theodore Ts'o <tytso@mit.edu>
Signed-off-by: Jeff Layton <jlayton@redhat.com>
Specify the 'clock-latency' property to avoid certain cpufreq governors
from refusing to work with the following error:
ondemand governor failed, too long transition latency of HW, fallback to performance governor
Reported-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Tested-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
If gpmc_cs_remap() fails we will get an error because we are calling
release_resource() on an uninitialized resource. Let's fix that by
checking the resource flags. And while at it, let's also make
gpmc_cs_delete_mem() use the res pointer that we already have to
avoid confusion.
Without this patch we can get the following error:
omap-gpmc 6e000000.gpmc: cannot remap GPMC CS 1 to 0x01000300
Unable to handle kernel NULL pointer dereference at virtual address 00000018
...
(gpmc_cs_free+0x94/0xc8)
(gpmc_probe_generic_child+0x178/0x1ec)
(gpmc_probe_dt+0x1bc/0x2cc)
(gpmc_probe+0x250/0x44c)
(platform_drv_probe+0x3c/0x6c)
(really_probe+0x74/0x208)
(driver_probe_device+0x34/0x50)
(bus_for_each_drv+0x60/0x8c)
(device_attach+0x80/0xa4)
(bus_probe_device+0x88/0xb0)
(device_add+0x320/0x450)
(of_platform_device_create_pdata+0x80/0x9c)
(of_platform_bus_create+0xd0/0x170)
(of_platform_bus_create+0x12c/0x170)
(of_platform_populate+0x60/0x98)
(pdata_quirks_init+0x30/0x48)
(customize_machine+0x20/0x48)
(do_one_initcall+0x2c/0x14c)
(do_basic_setup+0x98/0xd8)
(kernel_init_freeable+0x12c/0x1e0)
(kernel_init+0x8/0xf0)
(ret_from_fork+0x14/0x2c)
Code: e1a04000 e59f0070 eb195136 e5942010 (e5923018)
Cc: Pekon Gupta <pekon@ti.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: tony Lindgren <tony@atomide.com>
BeagleBoard xM A/B has an inverted usb hub enable line vs the xM C
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
[tony@atomide.com: updated for missing bracket]
Signed-off-by: Tony Lindgren <tony@atomide.com>
A few OMAP hwmod and clock fixes for v3.15-rc. Probably the most useful
fix is the AM43xx DPLL patch.
Basic build, boot, and PM test results are here:
http://www.pwsan.com/omap/testlogs/prcm-fixes-a-v3.15-rc/20140411130021/
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Merge tag 'for-v3.15-rc/omap-fixes-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.15/fixes
OMAP hwmod and clock fixes for v3.15-rc
A few OMAP hwmod and clock fixes for v3.15-rc. Probably the most useful
fix is the AM43xx DPLL patch.
Basic build, boot, and PM test results are here:
http://www.pwsan.com/omap/testlogs/prcm-fixes-a-v3.15-rc/20140411130021/
shiraz.hashim@st.com email-id doesn't exist anymore as he has left the
company. Replace ST's id with shiraz.linux.kernel@gmail.com.
It also updates .mailmap file to fix address for 'git shortlog'.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
commit a70143 (drivers: phy: usb3/pipe3: Adapt pipe3 driver to Generic PHY
Framework) moved phy-omap-usb3 driver in drivers/usb/phy to drivers/phy and
also renamed the file to phy-ti-pipe3. It also renamed the config from
OMAP_USB3 to TI_PIPE3 in Kconfig. However the config name was not changed in
omap2plus_defconfig. Fixed it here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
In "ARM: dts: am33xx: correcting dt node unit address for usb", the
usb_ctrl_mod and cppi41dma nodes were updated with the correct register
addresses. However, the dts files that reference these nodes were not
updated, and those devices are no longer being enabled.
This patch corrects the references for the affected dts files.
Signed-off-by: Leigh Brown <leigh@solinno.co.uk>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Remove all remaining uses of gpmc,device-nand that have been added since
the property was removed by commit f40739faba ("ARM: dts: OMAP2+:
Simplify NAND support").
Signed-off-by: Johan Hovold <jhovold@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Wrong documentation in pinmux description can be especially confusing.
Keep it proper.
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Do not try to initialize display for DT boot, since omapdss
is now initialized via Device Tree. Without this patch the
display subsystem does not properly come up.
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The correct bit is 24 for AHCLKX.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The USB3 PHY driver (ti-pipe3) was updated so that the relevant
clock phandles are expected in the DT node.
Provide the necessary clocks.
Reported-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The error emitted when mapping the pmu failed, wrongly mentions the sram.
Reported-by: Kent Borg <kentborg@borg.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The default behaviour of the uart-rx pins on the rk3188 is to be pulled up and
a lot of designs use diodes to even prevent them from being raised from the
outside.
Therefore change the rx-pin settings accordingly.
This also fixes a uart receive problem on mass production Radxa Rock boards.
Signed-off-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
To obtain exact pixel clocks, allow the DI clock selectors to influence
the PLLs that they are derived from.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Route the video PLL to the display interface clocks via the di_pre_sel
and di_sel muxes by default.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Fix typo of renesas,groups in the koeslch dt. The kernel has no
renesas,gpios but this should match renesas,groups.
Noticed thanks to similar fix for Lager by Rob Taylor and Ben Dooks.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
