The imx_pinctrl_soc_info structure content is never changed, so it can be
declared as 'const', like it is done on all other i.MX pinctrl drivers.
Make it 'const' in this driver too.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Link: https://lore.kernel.org/r/20210713122513.3112941-2-festevam@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The imx_pinctrl_soc_info structure content is never changed, so it can be
declared as 'const', like it is done on all other i.MX pinctrl drivers.
Make it 'const' in this driver too.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Link: https://lore.kernel.org/r/20210713122513.3112941-1-festevam@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The initialization of pin_reg is missing, causing the following build
warning:
drivers/pinctrl/freescale/pinctrl-imx8ulp.c:228:35: warning: 'pin_reg' is used uninitialized in this function [-Wuninitialized]
Initialize pin_reg the same way as it is done on vf610 and imx7ulp
to fix the problem.
Fixes: 16b343e8e0 ("pinctrl: imx8ulp: Add pinctrl driver support")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/20210723203242.88845-1-festevam@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
drivers/pinctrl/mediatek/pinctrl-mt8365.c:488:3-8: No need to set .owner here. The core will do it.
Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
Fixes: e94d8b6fb8 ("pinctrl: mediatek: add support for mt8365 SoC")
CC: Fabien Parent <fparent@baylibre.com>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20210626051550.GA37544@d0c207d51ce8
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The PWM pins on North Bridge on Armada 37xx can be configured into PWM
or GPIO functions. When in PWM function, each pin can also be configured
to drive low on 0 and tri-state on 1 (LED mode).
The current definitions handle this by declaring two pin groups for each
pin:
- group "pwmN" with functions "pwm" and "gpio"
- group "ledN_od" ("od" for open drain) with functions "led" and "gpio"
This is semantically incorrect. The correct definition for each pin
should be one group with three functions: "pwm", "led" and "gpio".
Change the "pwmN" groups to support "led" function.
Remove "ledN_od" groups. This cannot break backwards compatibility with
older device trees: no device tree uses it since there is no PWM driver
for this SOC yet. Also "ledN_od" groups are not even documented.
Fixes: b835d69530 ("pinctrl: armada-37xx: swap polarity on LED group")
Signed-off-by: Marek Behún <kabel@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210719112938.27594-1-kabel@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The if condition followed by BUG can be replaced to BUG_ON which is
more compact and formal in linux source.
Signed-off-by: Jason Wang <wangborong@cdjrlc.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20210624064913.41788-1-wangborong@cdjrlc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
New drivers:
- Last merge window we created a driver for the Ralink RT2880.
We are now moving the Ralink SoC pin control drivers out of the MIPS
architecture code and into the pin control subsystem. This concerns
RT288X, MT7620, RT305X, RT3883 and MT7621.
- Qualcomm SM6125 SoC pin control driver.
- Qualcomm spmi-gpio support for PM7325.
- Qualcomm spmi-mpp also handles PMI8994 (just a compatible string)
- Mediatek MT8365 SoC pin controller.
- New device HID for the AMD GPIO controller.
Improvements:
- Pin bias config support for a slew of Renesas pin controllers.
- Incremental improvements and non-urgent bug fixes to the Renesas
SoC drivers.
- Implement irq_set_wake on the AMD pin controller so we can wake
up from external pin events.
Misc:
- Devicetree bindings for the Apple M1 pin controller, we will probably
see a proper driver for this soon as well.
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Merge tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.14 kernel. Not so
much going on. No core changes, just drivers.
The most interesting would be that MIPS Ralink is migrating to pin
control and we have some bindings but not yet code for the Apple M1
pin controller.
New drivers:
- Last merge window we created a driver for the Ralink RT2880. We are
now moving the Ralink SoC pin control drivers out of the MIPS
architecture code and into the pin control subsystem. This concerns
RT288X, MT7620, RT305X, RT3883 and MT7621.
- Qualcomm SM6125 SoC pin control driver.
- Qualcomm spmi-gpio support for PM7325.
- Qualcomm spmi-mpp also handles PMI8994 (just a compatible string)
- Mediatek MT8365 SoC pin controller.
- New device HID for the AMD GPIO controller.
Improvements:
- Pin bias config support for a slew of Renesas pin controllers.
- Incremental improvements and non-urgent bug fixes to the Renesas
SoC drivers.
- Implement irq_set_wake on the AMD pin controller so we can wake up
from external pin events.
Misc:
- Devicetree bindings for the Apple M1 pin controller, we will
probably see a proper driver for this soon as well"
* tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (54 commits)
pinctrl: ralink: rt305x: add missing include
pinctrl: stm32: check for IRQ MUX validity during alloc()
pinctrl: zynqmp: some code cleanups
drivers: qcom: pinctrl: Add pinctrl driver for sm6125
dt-bindings: pinctrl: qcom: sm6125: Document SM6125 pinctrl driver
dt-bindings: pinctrl: mcp23s08: add documentation for reset-gpios
pinctrl: mcp23s08: Add optional reset GPIO
pinctrl: mediatek: fix mode encoding
pinctrl: mcp23s08: Fix missing unlock on error in mcp23s08_irq()
pinctrl: bcm: Constify static pinmux_ops
pinctrl: bcm: Constify static pinctrl_ops
pinctrl: ralink: move RT288X SoC pinmux config into a new 'pinctrl-rt288x.c' file
pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' file
pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file
pinctrl: ralink: move RT3883 SoC pinmux config into a new 'pinctrl-rt3883.c' file
pinctrl: ralink: move MT7621 SoC pinmux config into a new 'pinctrl-mt7621.c' file
pinctrl: ralink: move ralink architecture pinmux header into the driver
pinctrl: single: config: enable the pin's input
pinctrl: mtk: Fix mt8365 Kconfig dependency
pinctrl: mcp23s08: fix race condition in irq handler
...
Header 'rt305x.h' is ralink architecture dependent file where
other general definitions which are in 'ralink_regs.h' are
being used. This 'rt305x.h' is only being included in two
different files: 'rt305x.c' and 'pinctrl-rt305x.c'. When
file 'pinctrl-rt305x.c' is being compiled definitions in
'ralink_regs.h' are need to build it properly. Hence, add
missing include 'ralink_regs.h' in 'pinctrl-rt305x.c'
source to avoid compilation problems.
Fixes: 3a1b0ca5a8 ("pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210629143407.14703-1-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Considering the following irq_domain_ops call chain:
- .alloc() is called when a clients calls platform_get_irq() or
gpiod_to_irq()
- .activate() is called next, when the clients calls
request_threaded_irq()
Check for the IRQ MUX conflict during the first stage (alloc instead of
activate). This avoids to provide the client with an IRQ that can't be
used.
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20210617144602.2557619-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some minor code cleanups and updates which includes
- Mention module name under help in Kconfig.
- Remove extra lines and duplicate Pin range checks.
- Replace 'return ret' with 'return 0' in success path.
- Copyright year update.
- use devm_pinctrl_register() instead pinctrl_register() in probe.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Link: https://lore.kernel.org/r/1624273214-66849-1-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Each GPIO bank supports a variable number of lines which is usually 16, but
is less in some cases : this is specified by the last argument of the
"gpio-ranges" bank node property.
Report to the framework, the actual number of lines, so the libgpiod
gpioinfo command lists the actually existing GPIO lines.
Fixes: 1dc9d28915 ("pinctrl: stm32: add possibility to use gpio-ranges to declare bank range")
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20210617144629.2557693-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
device_for_each_child_node() bumps a reference counting of a returned variable.
We have to balance it whenever we return to the caller.
Fixes: 7e5ea974e6 ("pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO")
Cc: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20210606191940.29312-1-andy.shevchenko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add bias support for the R-Car H2, V2H, E2, V3M, and V3H, and
RZ/G1C, RZ/G1H, and RZ/G1E SoCs.
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Merge tag 'renesas-pinctrl-for-v5.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.14 (take two)
- Add bias support for the R-Car H2, V2H, E2, V3M, and V3H, and
RZ/G1C, RZ/G1H, and RZ/G1E SoCs.
The MCP23x port expander RESET# line can be connected to a host GPIO.
The optional reset-gpio must be set to LOW if the reset is asserted
at probing time.
On page 5 in the datasheet [0] the "Device Active After Reset high"
time is specified at 0 µs. Therefore no waiting is needed after the
reset transition.
[0] https://ww1.microchip.com/downloads/en/DeviceDoc/20001952C.pdf
Signed-off-by: Andreas Kaessens <akaessens@gmail.com>
Signed-off-by: Darian Biastoch <d.biastoch@gmail.com>
Link: https://lore.kernel.org/r/20210610132438.3085841-1-akaessens@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Enabling pin controller on Intel Alder Lake-M
The following is an automated git shortlog grouped by driver:
tigerlake:
- Add Alder Lake-M ACPI ID
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Merge tag 'intel-pinctrl-v5.14-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v5.14-1
* Enabling pin controller on Intel Alder Lake-M
The following is an automated git shortlog grouped by driver:
tigerlake:
- Add Alder Lake-M ACPI ID
Pin modes are encoded in the SoC data structure. Use that value to set
IES SMT.
Cc: Fabien Parent <fparent@baylibre.com>
Cc: Sean Wang <sean.wang@kernel.org>
Cc: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Cc: linux-mediatek@lists.infradead.org
Fixes: 696beef775 ("pinctrl: mediatek: move bit assignment")
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Link: https://lore.kernel.org/r/20210608150656.29007-1-matthias.bgg@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the missing unlock before return from function mcp23s08_irq()
in the error handling case.
v1-->v2:
remove the "return IRQ_HANDLED" line
Fixes: 897120d41e ("pinctrl: mcp23s08: fix race condition in irq handler")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zou Wei <zou_wei@huawei.com>
Link: https://lore.kernel.org/r/1623134048-56051-1-git-send-email-zou_wei@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It's currently not possible to select the SC8180x TLMM driver, due to it
selecting PINCTRL_MSM, rather than depending on the same. Fix this.
Fixes: 97423113ec ("pinctrl: qcom: Add sc8180x TLMM driver")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210608180702.2064253-1-bjorn.andersson@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These are only assigned, either directly or via the bcm63xx_pinctrl_soc
struct, to the pmxops field in the pinctrl_desc struct and never
modified, so make them const to allow the compiler to put them in
read-only memory.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20210605185908.39982-3-rikard.falkeborn@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These are only assigned, either directly or via the bcm63xx_pinctrl_soc
struct, to the pctlops field in the pinctrl_desc struct and never
modified, so make them const to allow the compiler to put them in
read-only memory.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20210605185908.39982-2-rikard.falkeborn@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Ralink architecture is making use of the header located in
'arch/mips/include/asm/mach-ralink/pinmux.h' to stablish the
mechanisms to make derived SoCs to set its pin functions and
groups. In order to move all architecture pinmux into a more
accurate place which is 'drivers/pinctrl/ralink' we have to
first of all move this file also there with a small modification
which creates 'rt2880_pinmux_init' function to allow SoCs pinctrl
drivers to pass its configuration to the common code located in
'pinctrl-rt2880.c' file.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210604115159.8834-2-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In 'rt2880_pmx_group_enable' driver is printing an error and returning
-EBUSY if a pin has been already enabled. This begets anoying messages
in the caller when this happens like the following:
rt2880-pinmux pinctrl: pcie is already enabled
mt7621-pci 1e140000.pcie: Error applying setting, reverse things back
To avoid this just print the already enabled message in the pinctrl
driver and return 0 instead to not confuse the user with a real
bad problem.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210604055337.20407-1-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It enables / disables the input buffer. As explained in the description
of 'enum pin_config_param' this does not affect the pin's ability to
drive output.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Acked-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20210602150420.18202-1-dariobin@libero.it
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This SoC needs to select PINCTRL_MTK or we can end up in
kernel compiles that miss some symbols.
Cc: Fabien Parent <fparent@baylibre.com>
Reported-by: kernel test robot <lkp@intel.com>
Fixes: e94d8b6fb8 ("pinctrl: mediatek: add support for mt8365 SoC")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Checking value of MCP_INTF in mcp23s08_irq suggests that the handler may be
called even when there is no interrupt pending.
But the actual interrupt could happened between reading MCP_INTF and MCP_GPIO.
In this situation we got nothing from MCP_INTF, but the event gets acknowledged
on the expander by reading MCP_GPIO. This leads to losing events.
Fix the problem by not reading any register until we see something in MCP_INTF.
The error was reproduced and fix tested on MCP23017.
Signed-off-by: Radim Pavlik <radim.pavlik@tbs-biometrics.com>
Link: https://lore.kernel.org/r/AM7PR06MB6769E1183F68DEBB252F665ABA3E9@AM7PR06MB6769.eurprd06.prod.outlook.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Implement support for pull-up (most pins, excl. DU_DOTCLKIN and EXTALR)
and pull-down (most pins, excl. JTAG) handling for the R-Car V3M SoC,
using the common R-Car bias handling.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/bcfad447624d874258a45a92554574b8fe9f712f.1619785375.git.geert+renesas@glider.be
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK)
handling for R-Car E2 and RZ/G1E SoCs, using the common R-Car bias
handling.
Note that on RZ/G1E, the "ASEBRK#/ACK" pin is called "ACK", but the code
doesn't handle that naming difference. Hence users should use the R-Car
naming in DTS files.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/f78da2ba937ce98ae9196f4ee54149a5214fd545.1619785375.git.geert+renesas@glider.be
Implement support for pull-up (most pins) and pull-down (EDBGREQ)
handling for the R-Car V2H SoC, using the common R-Car bias handling.
Note that the R-Car V2H Hardware User's Manual Rev. 1.00 says that
the LSI Pin Pull-Up Control Register 11 (PUPR11) controls pull-ups for
the {SCK,WS,SDATA}[01] pins. These are assumed to be typos, as R-Car
V2H has only Serial Sound Interface channels 3 and 4.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/48d2abdd63ee43ed99cb32ed4a5f4d76ba563162.1619785375.git.geert+renesas@glider.be
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK)
handling for R-Car H2 and RZ/G1H SoCs, using the common R-Car bias
handling.
Note that on RZ/G1H, the "ASEBRK#/ACK" pin is called "ACK", but the code
doesn't handle that naming difference. Hence users should use the R-Car
naming in DTS files.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/dde6e0b36a4e4494039a3466df208b5ec5c594ee.1619785375.git.geert+renesas@glider.be
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK)
handling for the RZ/G1C SoC, using the common R-Car bias handling.
Note that on RZ/G1C, the "ASEBRK#/ACK" pin is called "ACK", but the code
doesn't handle that naming difference. Hence users should use the R-Car
naming in DTS files.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/18c8ebf9fa9e239253a723857e9dffeec775db7e.1619785375.git.geert+renesas@glider.be
- Minor fixes and improvements.
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Merge tag 'renesas-pinctrl-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.14
- Minor fixes and improvements.
The bit needs offset to be defined which happens some lines
below. Looks like a bug. The kernel test robot complains:
drivers/pinctrl/mediatek/pinctrl-mtk-common.c:137:12:
warning: variable 'offset' is uninitialized when used here [-Wuninitialized]
bit = BIT(offset & pctl->devdata->mode_mask);
^~~~~~
Fix it up by reverting to what was done before.
Cc: Fabien Parent <fparent@baylibre.com>
Cc: Sean Wang <sean.wang@kernel.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Cc: linux-mediatek@lists.infradead.org
Fixes: 9f940d8ecf ("pinctrl: mediatek: don't hardcode mode encoding in common code")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The downstream .dts files only request two GPIO IRQs. Truncate the
array of parent IRQs when irq_of_parse_and_map returns 0.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20210521090158.26932-1-iivanov@suse.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix function name in pinctrl-single.c kernel-doc comment
to remove a warning found by clang_w1.
drivers/pinctrl/pinctrl-single.c:1523: warning: expecting prototype for
pcs_irq_handle(). Prototype was for pcs_irq_chain_handler() instead.
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Link: https://lore.kernel.org/r/1621998464-10918-1-git-send-email-yang.lee@linux.alibaba.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
AST2600 supports 2 SGPIO master interfaces and 2 SGPIO slave interfaces.
Current pinctrl driver only define the first sgpio master and slave
interfaces.
The second SGPIO master and slave interfaces should be added in
pinctrl driver as well.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20210525055308.31069-4-steven_lee@aspeedtech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
MT8365 encode the pins mode differently than other
MTK pinctrl drivers that use the PINCTRL_MTK common code.
Add 3 new fields in mtk_pinctrl_devdata in order to store how
pin modes are encoded into the register. At the
same time update all the pinctrl driver that depends on
CONFIG_PINCTRL_MTK.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20210519162409.3755679-2-fparent@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The at91_pinctrl_mux_ops struct is never modified by the driver. Make it
const wherever it is possible to allow the compiler to put the static
variables in read-only memory. Note that sam9x60_ops was already const,
but the const was cast away when the return value of of_match_device() was
cast to a pointer to a non-const struct at91_pinctrl_mux_ops.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20210512180140.33293-1-rikard.falkeborn@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
