Ben Skeggs
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0cdc3fdfb7
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drm/nouveau/fifo/gm107-: remove engines from mmu engine mapping array
These are specified by PTOP on Maxwell GPUs.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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2016-05-20 14:43:04 +10:00 |
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Ben Skeggs
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91419acf78
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drm/nouveau/fifo/gk104-: abstract mmu fault data structures
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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2016-05-20 14:43:04 +10:00 |
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Ben Skeggs
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98ac3f061a
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drm/nouveau/fifo/gk104-: subclass func
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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2016-05-20 14:43:04 +10:00 |
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Ben Skeggs
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db1eb52846
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drm/nouveau: s/gm204/gm200/ in a number of places
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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2016-03-14 10:13:12 +10:00 |
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Ben Skeggs
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13de7f4629
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drm/nouveau/fifo: convert to new-style nvkm_engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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2015-08-28 12:40:46 +10:00 |
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Alexandre Courbot
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3326060a17
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drm/nouveau/fifo: add GM20B fifo
GM20B has a 512-channels FIFO similar to GK104.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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2015-08-28 12:40:02 +10:00 |
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