accesses, inefficient and disfunctional code. The goal is to remove the
export of irq_to_desc() to prevent these things from creeping up again.
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Merge tag 'irq-core-2020-12-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner:
"This is the second attempt after the first one failed miserably and
got zapped to unblock the rest of the interrupt related patches.
A treewide cleanup of interrupt descriptor (ab)use with all sorts of
racy accesses, inefficient and disfunctional code. The goal is to
remove the export of irq_to_desc() to prevent these things from
creeping up again"
* tag 'irq-core-2020-12-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (30 commits)
genirq: Restrict export of irq_to_desc()
xen/events: Implement irq distribution
xen/events: Reduce irq_info:: Spurious_cnt storage size
xen/events: Only force affinity mask for percpu interrupts
xen/events: Use immediate affinity setting
xen/events: Remove disfunct affinity spreading
xen/events: Remove unused bind_evtchn_to_irq_lateeoi()
net/mlx5: Use effective interrupt affinity
net/mlx5: Replace irq_to_desc() abuse
net/mlx4: Use effective interrupt affinity
net/mlx4: Replace irq_to_desc() abuse
PCI: mobiveil: Use irq_data_get_irq_chip_data()
PCI: xilinx-nwl: Use irq_data_get_irq_chip_data()
NTB/msi: Use irq_has_action()
mfd: ab8500-debugfs: Remove the racy fiddling with irq_desc
pinctrl: nomadik: Use irq_has_action()
drm/i915/pmu: Replace open coded kstat_irqs() copy
drm/i915/lpe_audio: Remove pointless irq_to_desc() usage
s390/irq: Use irq_desc_kstat_cpu() in show_msi_interrupt()
parisc/irq: Use irq_desc_kstat_cpu() in show_interrupts()
...
New drivers:
- New driver for the Microchip Serial GPIO "SGPIO".
- Qualcomm SM8250 LPASS (Low Power Audio Subsystem) GPIO driver.
New subdrivers:
- Intel Lakefield subdriver.
- Intel Elkhart Lake subdriver.
- Intel Alder Lake-S subdriver.
- Qualcomm MSM8953 subdriver.
- Qualcomm SDX55 subdriver.
- Qualcomm SDX55 PMIC subdriver.
- Ocelot Luton SoC subdriver.
- Ocelot Serval SoC subdriver.
Modularization:
- The Meson driver can now be built as modules.
- The Qualcomm driver(s) can now be built as modules.
Incremental improvements:
- The Intel driver now supports pin configuration for GPIO-related
configurations.
- A bunch of Renesas PFC drivers have been augmented with support
for QSPI pins, groups and functions.
- Non-critical fixes to the irq handling in the Allwinner Sunxi
driver.
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Merge tag 'pinctrl-v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.11 kernel.
Drivers, drivers and drivers. Not a single core change.
Some new stuff, especially a bunch of new Intel, Qualcomm and Ocelot
SoCs.
As part of the modularization attempt, I applied one patch affecting
the firmware subsystem as a functional (not syntactic/semantic)
dependency and then it blew up in our face, so I had to revert it,
bummer. It will come in later, through that subsystem, I guess.
New drivers:
- New driver for the Microchip Serial GPIO "SGPIO".
- Qualcomm SM8250 LPASS (Low Power Audio Subsystem) GPIO driver.
New subdrivers:
- Intel Lakefield subdriver.
- Intel Elkhart Lake subdriver.
- Intel Alder Lake-S subdriver.
- Qualcomm MSM8953 subdriver.
- Qualcomm SDX55 subdriver.
- Qualcomm SDX55 PMIC subdriver.
- Ocelot Luton SoC subdriver.
- Ocelot Serval SoC subdriver.
Modularization:
- The Meson driver can now be built as modules.
- The Qualcomm driver(s) can now be built as modules.
Incremental improvements:
- The Intel driver now supports pin configuration for GPIO-related
configurations.
- A bunch of Renesas PFC drivers have been augmented with support for
QSPI pins, groups and functions.
- Non-critical fixes to the irq handling in the Allwinner Sunxi
driver"
* tag 'pinctrl-v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
pinctrl/spear: simplify the return expression of spear300_pinctrl_probe()
pinctrl: mediatek: simplify the return expression of mtk_pinconf_bias_disable_set_rev1()
dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add irq support
pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5)
pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings
pinctrl: qcom-pmic-gpio: Add support for pmx55
dt-bindings: pinctrl: qcom-pmic-gpio: Add pmx55 support
pinctrl: pinctrl-microchip-sgpio: Mark some symbols with static keyword
pinctrl: at91-pio4: Make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix build error
pinctrl: mtk: Fix low level output voltage issue
pinctrl: falcon: add missing put_device() call in pinctrl_falcon_probe()
pinctrl: actions: pinctrl-s500: Constify s500_padinfo[]
pinctrl: pinctrl-microchip-sgpio: Add OF config dependency
pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO
dt-bindings: pinctrl: Add bindings for pinctrl-microchip-sgpio driver
pinctrl: at91-pio4: add support for fewer lines on last PIO bank
pinctrl: sunxi: Always call chained_irq_{enter, exit} in sunxi_pinctrl_irq_handler
pinctrl: sunxi: Mark the irq bank not found in sunxi_pinctrl_irq_handler() with WARN_ON
pinctrl: sunxi: fix irq bank map for the Allwinner A100 pin controller
...
Here is the big staging and IIO driver pull request for 5.11-rc1
Lots of different things in here:
- loads of driver updates
- so many coding style cleanups
- new IIO drivers
- Android ION code is finally removed from the tree
- wimax drivers are moved to staging on their way out of the kernel
Nothing really exciting, just the constant grind of kernel development :)
All have been in linux-next for a while with no reported issues.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'staging-5.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
Pull staging / IIO driver updates from Greg KH:
"Here is the big staging and IIO driver pull request for 5.11-rc1
Lots of different things in here:
- loads of driver updates
- so many coding style cleanups
- new IIO drivers
- Android ION code is finally removed from the tree
- wimax drivers are moved to staging on their way out of the kernel
Nothing really exciting, just the constant grind of kernel development :)
All have been in linux-next for a while with no reported issues"
* tag 'staging-5.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (341 commits)
staging: olpc_dcon: Do not call platform_device_unregister() in dcon_probe()
staging: most: Fix spelling mistake "tranceiver" -> "transceiver"
staging: qlge: remove duplicate word in comment
staging: comedi: mf6x4: Fix AI end-of-conversion detection
staging: greybus: Add TODO item about modernizing the pwm code
pinctrl: ralink: add a pinctrl driver for the rt2880 family
dt-bindings: pinctrl: rt2880: add binding document
staging: rtl8723bs: remove ELEMENT_ID enum
staging: rtl8723bs: remove unused macros
staging: rtl8723bs: replace EID_EXTCapability
staging: rtl8723bs: replace EID_BSSIntolerantChlReport
staging: rtl8723bs: replace EID_BSSCoexistence
staging: rtl8723bs: replace _MME_IE_
staging: rtl8723bs: replace _WAPI_IE_
staging: rtl8723bs: replace _EXT_SUPPORTEDRATES_IE_
staging: rtl8723bs: replace _ERPINFO_IE_
staging: rtl8723bs: replace _CHLGETXT_IE_
staging: rtl8723bs: replace _COUNTRY_IE_
staging: rtl8723bs: replace _IBSS_PARA_IE_
staging: rtl8723bs: replace _TIM_IE_
...
This adds 'interrupt-controller' features for the signals available on
the Microchip SGPIO controller, however only for controller versions
on the Sparx5 platform (or later).
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20201209142753.683208-2-lars.povlsen@microchip.com
[Select GPIOLIB_IRQCHIP in Kconfig]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Mistakenly the buffers (input and output) become enabled together for a short
period of time during GPIO request. This is problematic, because instead of
initial motive to disable them in the commit af7e3eeb84
("pinctrl: intel: Disable input and output buffer when switching to GPIO"),
the driven value on the pin, which might be used as an IRQ line, brings
firmwares of some touch pads to an awkward state that needs a full power off
to recover. Fix this, as stated in the culprit commit, by disabling the buffers.
Fixes: af7e3eeb84 ("pinctrl: intel: Disable input and output buffer when switching to GPIO")
BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=210497
Reported-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Link: https://lore.kernel.org/r/20201208182403.40435-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These Socs have 1-3 banks of 8-32 gpios. Rather then setting the muxing of each
pin individually, these socs have mux groups that when set will effect 1-N pins.
Pin groups have a 2, 4 or 8 different muxes.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20201208075523.7060-3-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Commit 6726fbff19bf ("pinctrl: aspeed: Fix GPI only function problem.")
fixes access to GPIO banks T and U on the AST2600. Both banks contain
input-only pins and the GPIO pin function is named GPITx and GPIUx
respectively. Unfortunately the fix had a negative impact on GPIO banks
D and E for the AST2400 and AST2500 where the GPIO pass-through
functions take similar "GPI"-style names. The net effect on the older
SoCs was that when the GPIO subsystem requested a pin in banks D or E be
muxed for GPIO, they were instead muxed for pass-through mode.
Mistakenly muxing pass-through mode e.g. breaks booting the host on
IBM's Witherspoon (AC922) platform where GPIOE0 is used for FSI.
Further exploit the names in the provided expression structure to
differentiate pass-through from pin-specific GPIO modes.
This follow-up fix gives the expected behaviour for the following tests:
Witherspoon BMC (AST2500):
1. Power-on the Witherspoon host
2. Request GPIOD1 be muxed via /sys/class/gpio/export
3. Request GPIOE1 be muxed via /sys/class/gpio/export
4. Request the balls for GPIOs E2 and E3 be muxed as GPIO pass-through
("GPIE2" mode) via a pinctrl hog in the devicetree
Rainier BMC (AST2600):
5. Request GPIT0 be muxed via /sys/class/gpio/export
6. Request GPIU0 be muxed via /sys/class/gpio/export
Together the tests demonstrate that all three pieces of functionality
(general GPIOs via 1, 2 and 3, input-only GPIOs via 5 and 6, pass-through
mode via 4) operate as desired across old and new SoCs.
Fixes: 9b92f5c51e ("pinctrl: aspeed: Fix GPI only function problem.")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Tested-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Cc: Billy Tsai <billy_tsai@aspeedtech.com>
Cc: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20201126063337.489927-1-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.
This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:
TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13]
This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20201202163443.26499-3-srinivas.kandagatla@linaro.org
[Add some dependencies]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix the following sparse warnings:
drivers/pinctrl/pinctrl-microchip-sgpio.c:63:31: warning: symbol 'properties_luton' was not declared. Should it be static?
drivers/pinctrl/pinctrl-microchip-sgpio.c:68:31: warning: symbol 'properties_ocelot' was not declared. Should it be static?
drivers/pinctrl/pinctrl-microchip-sgpio.c:73:31: warning: symbol 'properties_sparx5' was not declared. Should it be static?
Signed-off-by: Zou Wei <zou_wei@huawei.com>
Link: https://lore.kernel.org/r/1606218173-3722-1-git-send-email-zou_wei@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If CONFIG_HAS_IOMEM is not set, devm_platform_ioremap_resource() will
be not built in drivers/base/platform.c and then there exists a build
error about undefined reference to "devm_platform_ioremap_resource"
in pinctrl-at91-pio4.c under COMPILE_TEST and CONFIG_PINCTRL_AT91PIO4,
make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix it.
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Link: https://lore.kernel.org/r/1606209423-4742-1-git-send-email-yangtiezhu@loongson.cn
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch is used to fix low level output voltage issue.
A pin is changed from input pull-up to output high.
The Dout value of the pin is default as 0.
If we change the direction of the pin before the dout value of the pin,
It maybe produce a low level output voltage between "input pull-up" and
"output high".
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Link: https://lore.kernel.org/r/20201120093058.7248-2-zhiyong.tao@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
if of_find_device_by_node() succeed, pinctrl_falcon_probe() doesn't have
a corresponding put_device(). Thus add put_device() to fix the exception
handling for this function implementation.
Fixes: e316cb2b16 ("OF: pinctrl: MIPS: lantiq: adds support for FALCON SoC")
Signed-off-by: Yu Kuai <yukuai3@huawei.com>
Link: https://lore.kernel.org/r/20201119011219.2248232-1-yukuai3@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
s500_padinfo[] is never modified and should be made 'const' to allow
the compiler to optimize code generation, i.e. put it in the text
section instead of the data section.
Before:
text data bss dec hex filename
12503 5088 0 17591 44b7 drivers/pinctrl/actions/pinctrl-s500.o
After:
text data bss dec hex filename
14435 3156 0 17591 44b7 drivers/pinctrl/actions/pinctrl-s500.o
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Link: https://lore.kernel.org/r/24505deb08d050eb4ce38f186f4037d7541ea217.1605722628.git.cristian.ciocaltea@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pinctrl-microchip-sgpio driver needs OF support, so add that to
Kconfig.
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Link: https://lore.kernel.org/r/20201125122014.11237-1-lars.povlsen@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO
(SGPIO) device used in various SoC's.
The driver is added as a pinctrl driver, albeit only having just GPIO
support currently. The hardware supports other functions that will be
added following.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20201113145151.68900-3-lars.povlsen@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Only a cleanup of unneeded breaks.
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Merge tag 'samsung-pinctrl-5.11' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
Samsung pinctrl drivers changes for v5.11
Only a cleanup of unneeded breaks.
- Add QSPI pin groups on R-Car E3, H3, M3-W/W+, and M3-N,
- A small fix for a Clang warning.
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Merge tag 'renesas-pinctrl-for-v5.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.11 (take two)
- Add QSPI pin groups on R-Car E3, H3, M3-W/W+, and M3-N,
- A small fix for a Clang warning.
Some products, like sama7g5, do not have a full last bank of PIO lines.
In this case for example, sama7g5 only has 8 lines for the PE bank.
PA0-31, PB0-31, PC0-31, PD0-31, PE0-7, in total 136 lines.
To cope with this situation, added a data attribute that is product dependent,
to specify the number of lines of the last bank.
In case this number is different from the macro ATMEL_PIO_NPINS_PER_BANK,
adjust the total number of lines accordingly.
This will avoid advertising 160 lines instead of the actual 136, as this
product supports, and to avoid reading/writing to invalid register addresses.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Link: https://lore.kernel.org/r/20201113132429.420940-1-eugen.hristev@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Add Intel Alder Lake-S pin controller support
* Add Intel Elkhart Lake pin controller support
* Add Intel Lakefield driver pin controller support
* Miscellaneous fixes for Intel Lynxpoint driver
The following is an automated git shortlog grouped by driver:
intel:
- Add Intel Alder Lake-S pin controller support
- Add Intel Elkhart Lake pin controller support
- Add blank line before endif in Kconfig
- Add Intel Lakefield pin controller support
lynxpoint:
- Enable pin configuration setting for GPIO chip
- Use defined constant for disabled bias explicitly
- Unify initcall location in the code
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Merge tag 'intel-pinctrl-v5.11-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v5.11-1
* Add Intel Alder Lake-S pin controller support
* Add Intel Elkhart Lake pin controller support
* Add Intel Lakefield driver pin controller support
* Miscellaneous fixes for Intel Lynxpoint driver
The following is an automated git shortlog grouped by driver:
intel:
- Add Intel Alder Lake-S pin controller support
- Add Intel Elkhart Lake pin controller support
- Add blank line before endif in Kconfig
- Add Intel Lakefield pin controller support
lynxpoint:
- Enable pin configuration setting for GPIO chip
- Use defined constant for disabled bias explicitly
- Unify initcall location in the code
It is found on many allwinner soc that there is a low probability that
the interrupt status cannot be read in sunxi_pinctrl_irq_handler. This
will cause the interrupt status of a gpio bank to always be active on
gic, preventing gic from responding to other spi interrupts correctly.
So we should call the chained_irq_* each time enter sunxi_pinctrl_irq_handler().
Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/85263ce8b058e80cea25c6ad6383eb256ce96cc8.1604988979.git.frank@allwinnertech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The interrupt descriptor cannot be found in the interrupt processing
function, and this situation cannot happen when the system is running
normally. It doesn't seem right to return directly to the status of not
handling gic. In this case, it must be a bug, let's mark it with
WARN_ON.
Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Link: https://lore.kernel.org/r/470ebae22fc5434ad5409c4f6e29255467b3cef6.1604988979.git.frank@allwinnertech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
One fixup following my patch commit be117ca322 ("pinctrl:
qcom: Kconfig: Rework PINCTRL_MSM to be a depenency rather then
a selected config") being queued in LinusW's tree, as a new
config entry was added for the msm8953 that also needs the
change.
Applies to LinusW's pinctrl devel tree.
Signed-off-by: John Stultz <john.stultz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Prasad Sodagudi <psodagud@codeaurora.org>
Cc: Vladimir Lypak <junak.pub@gmail.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Link: https://lore.kernel.org/r/20201110215619.86076-1-john.stultz@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Fix HOSTSW_OWN offset and unhide SPI group of pins on Jasper Lake
* Fix debounce configuration on Baytrail when it's turned off
* Fix default bias setting on Merrifield
The following is an automated git shortlog grouped by driver:
baytrail:
- Avoid clearing debounce value when turning it off
jasperlake:
- Fix HOSTSW_OWN offset
- Unhide SPI group of pins
merrifield:
- Set default bias in case no particular value given
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Merge tag 'intel-pinctrl-v5.10-3' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into fixes
intel-pinctrl for v5.10-3
* Fix HOSTSW_OWN offset and unhide SPI group of pins on Jasper Lake
* Fix debounce configuration on Baytrail when it's turned off
* Fix default bias setting on Merrifield
The following is an automated git shortlog grouped by driver:
baytrail:
- Avoid clearing debounce value when turning it off
jasperlake:
- Fix HOSTSW_OWN offset
- Unhide SPI group of pins
merrifield:
- Set default bias in case no particular value given
Since commit 4b563a0666 ("ARM: imx: Remove imx21 support") the imx21
SoC is no longer supported.
Get rid of its pinctrl driver too, which is now unused.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Link: https://lore.kernel.org/r/20201110190210.29376-1-festevam@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add remaining video-in (VIN) pin groups on R-Car H2 and RZ/G1H,
- Image size optimizations and code consolidations,
- Minor fixes and improvements.
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Merge tag 'renesas-pinctrl-for-v5.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.11
- Add remaining video-in (VIN) pin groups on R-Car H2 and RZ/G1H,
- Image size optimizations and code consolidations,
- Minor fixes and improvements.
Baytrail pin control has a common register to set up debounce timeout.
When a pin configuration requested debounce to be disabled, the rest
of the pins may still want to have debounce enabled and thus rely on
the common timeout value. Avoid clearing debounce value when turning
it off for one pin while others may still use it.
Fixes: 658b476c74 ("pinctrl: baytrail: Add debounce configuration")
Depends-on: 04ff5a095d ("pinctrl: baytrail: Rectify debounce support")
Depends-on: 827e1579e1 ("pinctrl: baytrail: Rectify debounce support (part 2)")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
When GPIO library asks pin control to set the bias, it doesn't pass
any value of it and argument is considered boolean (and this is true
for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual
drivers must behave well, when they got the resistance value of 1 Ohm,
i.e. transforming it to sane default.
In case of Intel Merrifield pin control hardware the 20 kOhm sounds plausible
because it gives a good trade off between weakness and minimization of leakage
current (will be only 50 uA with the above choice).
Fixes: 4e80c8f505 ("pinctrl: intel: Add Intel Merrifield pin controller support")
Depends-on: 2956b5d94a ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
GPIOs that attempt to use interrupts get thwarted with a message like:
"pin 161 cannot be used as IRQ" (for instance with SD_CD). This is because
the HOSTSW_OWN offset is incorrect, so every GPIO looks like it's
owned by ACPI.
Fixes: e278dcb704 ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Cc: stable@vger.kernel.org
Signed-off-by: Evan Green <evgreen@chromium.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
If the group of pins is hidden in the pin list it affects
the register offset calculation despite fixed GPIO base.
Hence, the offsets of all pins after the hidden group
are broken. Instead we have to unhide the group and use a flag
to exclude it from GPIO number space.
Fixes: e278dcb704 ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Reported-by: Divagar Mohandass <divagar.mohandass@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Baytrail pin control has a common register to set up debounce timeout.
When a pin configuration requested debounce to be disabled, the rest
of the pins may still want to have debounce enabled and thus rely on
the common timeout value. Avoid clearing debounce value when turning
it off for one pin while others may still use it.
Fixes: 658b476c74 ("pinctrl: baytrail: Add debounce configuration")
Depends-on: 04ff5a095d ("pinctrl: baytrail: Rectify debounce support")
Depends-on: 827e1579e1 ("pinctrl: baytrail: Rectify debounce support (part 2)")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
The only usage of sh73a0_vccq_mc0_ops is to assign its address to the
ops field in the regulator_desc struct, which is a const pointer. Make
it const to allow the compiler to put it in read-only memory.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20201109221012.177478-1-rikard.falkeborn@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
On SuperH and ARM SH/R-Mobile SoCs, the pin control driver handles
GPIOs, too. To reduce code size when compiling a kernel supporting only
modern SoCs, most, but not all, of the GPIO functionality is protected
by checks for CONFIG_PINCTRL_SH_FUNC_GPIO.
Factor out the remaining parts when not needed:
1. sh_pfc_soc_info.{in,out}put describe GPIO pins that have input
resp. output capabilities (SuperH and SH/R-Mobile).
2. sh_pfc_soc_info.gpio_irq{,_size} describe the mapping from GPIO
pins to interrupt numbers (SH/R-Mobile).
3. sh_pfc_gpio_set_direction() configures GPIO direction, called from
the GPIO driver through pinctrl_gpio_direction_{in,out}put()
(SH/R-Mobile). Unfortunately this function cannot just be moved to
drivers/pinctrl/renesas/gpio.c, as it relies on knowledge of
sh_pfc_pinctrl, which is internal to
drivers/pinctrl/renesas/pinctrl.c.
While code size reduction is minimal, this does help in documenting
depencies.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-9-geert+renesas@glider.be
Currently, the rcar_pinmux_[gs]et_bias() helpers handle only SoCs that
have separate LSI Pin Pull-Enable (PUEN) and Pull-Up/Down Control (PUD)
registers, like R-Car Gen3 and RZ/G2. Update the function to handle
SoCs that have only LSI Pin Pull-Up Control Register (PUPR), like R-Car
Gen1/Gen2 and RZ/G1.
Reduce code duplication by converting the R-Car M1A pin control driver
to use the common handler.
Note that this changes behavior in case the (invalid!) option
"bias-pull-down" is used in an R-Car M1A DTS: before, it was ignored
silently; after this change, it is considered the same as
"bias-pull-up".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-8-geert+renesas@glider.be
The handling of the LSI Pin Pull-Up Control Registers (PUPR) on R-Car
M1A uses register offsets instead of register physical addresses.
This is different from the handling on other R-Car parts.
Convert the bias handling from register offsets to physical addresses.
This increases uniformity, and prepares for consolidation of the bias
handling.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-7-geert+renesas@glider.be
Shrink sh_pfc_pin_config from 8 to 2 bytes:
- The mux_set flag can be removed, as a non-zero mark value means the
same (zero = PINMUX_RESERVED is an invalid mark value),
- The gpio_enabled flag needs only a single bit,
- Mark values are small integers, and can easily fit in a 15-bit
bitfield.
This saves 6 bytes per pin when allocating the sh_pfc_pinctrl.configs
array, i.e. it reduces run-time memory consumption by ca. 1.5 KiB.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-5-geert+renesas@glider.be
On arm64, pointer size and alignment is 64-bit, hence a 4-byte hole is
present in between the enum_id and name members of the sh_pfc_pin
structure. Get rid of this hole by sorting the structure's members by
decreasing size.
This saves up to 1.5 KiB per enabled SoC, and reduces the size of a
kernel including support for all R-Car Gen3 SoCs by more than 10 KiB.
This has no size impact on SH and arm32.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-4-geert+renesas@glider.be
