Commit Graph

588658 Commits

Author SHA1 Message Date
Xing Zheng
f73b5042b9 clk: rockchip: add general gpu soft-reset on rk3399
Add the id for the general gpu soft-reset, that got documented only in
newer TRM versions.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25 22:46:53 +02:00
Xing Zheng
f3d40914d3 clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399
The gate bits of the i2c4 and i2c8 are incorrect due to the manual
error, we need to fix them.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25 21:52:32 +02:00
Jens Kuske
ff2bb89335 clk: sunxi: Let divs clocks read the base factor clock name from devicetree
Currently, the sunxi clock driver gets the name for the base factor clock
of divs clocks from the name field in factors_data. This prevents reusing
of the factor clock for clocks with same properties, but different name.

This commit makes the divs setup function try to get a name from
clock-output-names in the devicetree. It also removes the name field where
possible and merges the sun4i PLL5 and PLL6 clocks.

[Andre: Make temporary name allocation dynamic.]

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-04-25 10:57:45 +02:00
Colin Ian King
b8199ff31f clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type
fix spelling mistake, unsucessful -> unsuccessful

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-25 09:34:03 +02:00
Maxime Ripard
cc510c736b clk: sunxi: Add TCON channel1 clock
The TCON is a controller generating the timings to output videos signals,
acting like both a CRTC and an encoder.

It has two channels depending on the output, each channel being driven by
its own clock (and own clock controller).

Add a driver for the channel 1 clock.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-22 00:29:24 +02:00
Maxime Ripard
fa4d0ca104 clk: sunxi: Add PLL3 clock
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
PLL7, clocked from a 3MHz oscillator, that drives the display related
clocks (GPU, display engine, TCON, etc.)

Add a driver for it.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-04-22 00:29:23 +02:00
Maxime Ripard
7f2ea3847d dt-bindings: clk: sun5i: add DRAM gates compatible
The Allwinner SoCs have a gate controller to gate the access to the DRAM
clock to the some devices that need to access the DRAM directly (mostly
display / image related IPs).

Use a simple gates driver to support the one found in the A13 / R8 SoCs.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-04-22 00:29:23 +02:00
Vaishali Thakkar
f4b9ef653c clk: sunxi: Use resource_size
Use the function resource_size instaed of explicit computation.

Problem found using Coccinelle.

Signed-off-by: Vaishali Thakkar <vaishali.thakkar@oracle.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-04-22 00:29:22 +02:00
Jean-Francois Moine
5ed400dd96 clk: sunxi: Add sun6i/8i display support
Add the clock type which is used by the sun6i/8i families for video display.

Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-04-22 00:29:22 +02:00
Andrea Venturi
8f0767611a clk: sunxi: mod1 clock should modify it's parent
add CLK_SET_RATE_PARENT to modify the rate on clk upstream

Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-04-22 00:29:21 +02:00
Stephen Boyd
58657d189a Merge branch 'clk-hw-register' (early part) into clk-next
* 'clk-hw-register' (early part):
  clk: fixed-rate: Add hw based registration APIs
  clk: gpio: Add hw based registration APIs
  clk: composite: Add hw based registration APIs
  clk: fractional-divider: Add hw based registration APIs
  clk: fixed-factor: Add hw based registration APIs
  clk: mux: Add hw based registration APIs
  clk: gate: Add hw based registration APIs
  clk: divider: Add hw based registration APIs
  clkdev: Add clk_hw based registration APIs
  clk: Add clk_hw OF clk providers
  clk: Add {devm_}clk_hw_{register,unregister}() APIs
  clkdev: Remove clk_register_clkdevs()
2016-04-21 14:47:18 -07:00
Stephen Boyd
e9471c4ecf Merge branch 'clk-composite-unregister' into clk-next
* clk-composite-unregister:
  clk: composite: Add unregister function
2016-04-21 14:43:56 -07:00
Maxime Ripard
92a39d9043 clk: composite: Add unregister function
The composite clock didn't have any unregistration function, which forced
us to use clk_unregister directly on it.

While it was already not great from an API point of view, it also meant
that we were leaking the clk_composite structure allocated in
clk_register_composite.

Add a clk_unregister_composite function to fix this.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-21 14:43:28 -07:00
Neil Armstrong
624b5ea624 dt-bindings: Add Oxford Semiconductor OXNAS Standard Clocks bindings
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-21 14:20:15 -07:00
Neil Armstrong
0bbd72b4c6 clk: Add Oxford Semiconductor OXNAS Standard Clocks
Add Oxford Semiconductor OXNAS SoC Family Standard Clocks support.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[sboyd@codeaurora.org: Drop NULL/continue check in registration
loop]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-21 14:20:07 -07:00
Stephen Boyd
bb4399b8a5 clk: renesas: R-Car SYSC PM Domain Preparation
- Export the CPG/MSSR and CPG/MSTP attach/detach_dev callbacks, so
     they can be called by the R-Car SYSC PM Domain driver.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJXF2zRAAoJEEgEtLw/Ve77lQkP/0ePeLyPLr2kqmMWe3+5MaVe
 suKU0i3GAV1fQJpl6Z3CibiDdjXrT9/7S+VVDaBme3VHwlE22QvBD0f2yn4RyL11
 f5wJIyCf1TXMdfsL0MSnX+6efcfwfdDDgUe/aoMj2ybOwOfFwIbKEPDhVjkMeqQo
 OcbIG8qBN0Hh237Lkb70SC0Oc27djSPpdoxd5+3B5ytpHo1q0ER1qQfdwy0MmG2J
 vtcXnZxHoigxk6uanH8BwpdYbFhhRA+KRmyxfS4MYmOVdaVvUZPCddbLBDfcE6d9
 xYpno+7TKVYni9rwd48Vq0EASVkRSyBJplCfLYOWCieIvrdHbFVpxGFTeW+uxzBS
 b+mRKnuM7fGm8j5At+i7bVbKVAXVvWaRr9K4j4E/XukT2B1/dNfRoc0HEBJzNsnO
 +S/X2JoHDyeiGva8cESlnQgO2rE9YiktxMVPX+Ey0k0ab7UigM6SzUle7wt1PVOg
 PfNLfJUkGxv77GpPKjhb/BbhImBmMIBLeHKOwMKM8WFCeLUjk6h8CsPFmsFPgAE7
 rTk87G1bMWBjjpk0d0nTggIStErF91yTZW+4kSMK9LRg+1//b+NO3xe9kQABLcmX
 5qaZoQDRqHiq+6loqsOW0xzvMjAYOxUmvE0oeqLamX20Qg5SzZmwcMtC+JceWSFG
 GE5VOJ8cBWcaBLFUmCmq
 =jmQf
 -----END PGP SIGNATURE-----

Merge tag 'clk-renesas-for-v4.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

clk: renesas: R-Car SYSC PM Domain Preparation

  - Export the CPG/MSSR and CPG/MSTP attach/detach_dev callbacks, so
    they can be called by the R-Car SYSC PM Domain driver.

* tag 'clk-renesas-for-v4.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev()
  clk: renesas: mstp: Provide dummy attach/detach_dev callbacks
  clk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP support
2016-04-20 11:44:03 -07:00
Stephen Boyd
0f05db651d Fix quite some checkpatch warnings in the newly added
rk3399 header and also in the clock code itself.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABCAAGBQJXFzXaAAoJEPOmecmc0R2BfoIH/jzxzuOFb7oMIEjWA1Dlv6ev
 I9l63Pi5+/BGXMXkuvBCpyVKRk9T7jyAkQbvMuoo6ELOmEtn2AX4BC7Pq+xok7Xz
 WZZQY/+nkYaAjJ6GscLpqWtNlhwCY0Ms/1WOp9DwTwcDztiTJaa9iQf5CELEJMhg
 RfANV2DIi9mNh+Nx4JIQi2e01tN2EXUsSNH8NVKTqfZKR/hvb9KO3qQWQzGdgqPr
 jNaAuVIq1iOIV0fBD7X8WJwQ2JqmrP7UsvIAXYk46E53jSk5RvnrGIvFp23pu0Jc
 0a677jCpx09en6LLPXQOwgtx687hChP5HT466BXo241daJkX4isDKAx430p7hGY=
 =99uY
 -----END PGP SIGNATURE-----

Merge tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull some checkpatch silencers from Heiko Stuebner:

Fix quite some checkpatch warnings in the newly added
rk3399 header and also in the clock code itself.

* tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: fix checkpatch warning in core code
  clk: rockchip: drop unnecessary header comment
  clk: rockchip: reign in some overly long lines in the rk3399 controller
  clk: rockchip: fix checkpatch errors in rk3399 dt-binding header
2016-04-20 11:41:37 -07:00
Heiko Stuebner
03ae174786 clk: rockchip: fix checkpatch warning in core code
We seem to have accumulated a bunch of checkpatch warnings, with mainly
overlong lines and two unnecessary allocation error messages.
Most were introduced with the recent multi-controller-support but some
were quite a bit older.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-20 09:53:39 +02:00
Geert Uytterhoeven
2066390ad4 clk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev()
The R-Car SYSC PM Domain driver has to power manage devices in power
areas using clocks. To reuse code and to share knowledge of clocks
suitable for power management, this is ideally done through the existing
cpg_mssr_attach_dev() and cpg_mssr_detach_dev() callbacks.

Hence these callbacks can no longer rely on their "domain" parameter
pointing to the CPG/MSSR Clock Domain. To handle this, keep a pointer to
the clock domain in a static variable. cpg_mssr_attach_dev() has to
support probe deferral, as the R-Car SYSC PM Domain may be initialized,
and devices may be added to it, before the CPG/MSSR Clock Domain is
initialized.

Dummy callbacks are provided for the case where CPG/MSTP support is not
included, so the rcar-sysc driver won't have to care about this.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-04-20 09:17:07 +02:00
Geert Uytterhoeven
12524e348b clk: renesas: mstp: Provide dummy attach/detach_dev callbacks
Provide dummy cpg_mstp_{at,de}tach_dev() PM Domain callbacks if CPG/MSTP
support is not included, so the rcar-sysc driver won't have to care
about this.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-04-20 09:17:04 +02:00
Geert Uytterhoeven
a5bd7f7a72 clk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP support
Currently the decision whether to build the renesas-cpg-mssr and
clk-mstp drivers is handled by Makefile logic.  However, the rcar-sysc
driver will need to know whether CPG/MSSR and/or CPG/MSTP support are
available or not.

To avoid having to duplicate this logic, move it to Kconfig. Provide
non-visible CLK_RENESAS_CPG_MSSR and CLK_RENESAS_CPG_MSTP Kconfig
symbols, which can be used by both Makefiles and C code.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-04-20 09:16:58 +02:00
Eric Anholt
e708b383f4 clk: bcm2835: Fix PLL poweron
In poweroff, we set the reset bit and the power down bit, but only
managed to unset the reset bit for poweron.  This meant that if HDMI
did -EPROBE_DEFER after it had grabbed its clocks, we'd power down the
PLLH (that had been on at boot time) and never recover.

Signed-off-by: Eric Anholt <eric@anholt.net>
Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 18:56:17 -07:00
Eric Anholt
286259ef4b clk: bcm2835: Fix compiler warnings on 64-bit builds
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 18:56:16 -07:00
Julia Lawall
3432a2e397 clk: qoriq: add __init attribute
Add __init attribute on a function that is only called from other __init
functions and that is not inlined, at least with gcc version 4.8.4 on an
x86 machine with allyesconfig.  Currently, the function is put in the
.text.unlikely segment.  Declaring it as __init will cause it to be put in
the .init.text and to disappear after initialization.

The result of objdump -x on the function before the change is as follows:

0000000000000000 l     F .text.unlikely 0000000000000071 sysclk_from_fixed.constprop.5

And after the change it is as follows:

0000000000000480 l     F .init.text	000000000000006c sysclk_from_fixed.constprop.5

Done with the help of Coccinelle.  The semantic patch checks for local
static non-init functions that are called from an __init function and are
not called from any other function.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 18:56:15 -07:00
Peter Ujfalusi
660e155193 clk: ti: dra7-atl-clock: Fix of_node reference counting
of_find_node_by_name() will call of_node_put() on the node so we need to
get it first to avoid warnings.
The cfg_node needs to be put after we have finished processing the
properties.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 18:56:14 -07:00
Stephen Boyd
26ef56be9e clk: fixed-rate: Add hw based registration APIs
Add registration APIs in the clk fixed-rate code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 16:57:12 -07:00
Stephen Boyd
b120743a64 clk: gpio: Add hw based registration APIs
Add registration APIs in the clk gpio code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 16:56:28 -07:00
Stephen Boyd
49cb392d36 clk: composite: Add hw based registration APIs
Add registration APIs in the clk composite code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 16:56:28 -07:00
Stephen Boyd
39b44cff4a clk: fractional-divider: Add hw based registration APIs
Add registration APIs in the clk fractional divider code to
return struct clk_hw pointers instead of struct clk pointers.
This way we hide the struct clk pointer from providers unless
they need to use consumer facing APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 16:56:28 -07:00
Stephen Boyd
0759ac8a73 clk: fixed-factor: Add hw based registration APIs
Add registration APIs in the clk fixed-factor code to return
struct clk_hw pointers instead of struct clk pointers. This way
we hide the struct clk pointer from providers unless they need to
use consumer facing APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 16:56:28 -07:00
Stephen Boyd
264b317197 clk: mux: Add hw based registration APIs
Add registration APIs in the clk mux code to return struct clk_hw
pointers instead of struct clk pointers. This way we hide the
struct clk pointer from providers unless they need to use
consumer facing APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 16:55:01 -07:00
Stephen Boyd
e270d8cb13 clk: gate: Add hw based registration APIs
Add registration APIs in the clk gate code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 16:55:01 -07:00
Stephen Boyd
eb7d264f3b clk: divider: Add hw based registration APIs
Add registration APIs in the clk divider code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 16:55:01 -07:00
Stephen Boyd
e4f1b49bda clkdev: Add clk_hw based registration APIs
Now that we have a clk registration API that doesn't return
struct clks, we need to have some way to hand out struct clks via
the clk_get() APIs that doesn't involve associating struct clk
pointers with a struct clk_lookup. Luckily, clkdev already
operates on struct clk_hw pointers, except for the registration
facing APIs where it converts struct clk pointers into struct
clk_hw pointers almost immediately.

Let's add clk_hw based registration APIs so that we can skip the
conversion step and provide a way for clk provider drivers to
operate exclusively on clk_hw structs. This way we clearly
split the API between consumers and providers.

Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 16:54:26 -07:00
Stephen Boyd
0861e5b8cf clk: Add clk_hw OF clk providers
Now that we have a clk registration API that doesn't return
struct clks, we need to have some way to hand out struct clks via
the clk_get() APIs that doesn't involve associating struct clk
pointers with an OF node. Currently we ask the OF provider to
give us a struct clk pointer for some clkspec, turn that struct
clk into a struct clk_hw and then allocate a new struct clk to
return to the caller.

Let's add a clk_hw based OF provider hook that returns a struct
clk_hw directly, so that we skip the intermediate step of
converting from struct clk to struct clk_hw. Eventually when
we've converted all OF clk providers to struct clk_hw based APIs
we can remove the struct clk based ones.

It should also be noted that we change the onecell provider to
have a flex array instead of a pointer for the array of clk_hw
pointers. This allows providers to allocate one structure of the
correct length in one step instead of two.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 16:52:22 -07:00
Stephen Boyd
4143804c4f clk: Add {devm_}clk_hw_{register,unregister}() APIs
We've largely split the clk consumer and provider APIs along
struct clk and struct clk_hw, but clk_register() still returns a
struct clk pointer for each struct clk_hw that's registered.
Eventually we'd like to only allocate struct clks when there's a
user, because struct clk is per-user now, so clk_register() needs
to change.

Let's add new APIs to register struct clk_hws, but this time
we'll hide the struct clk from the caller by returning an int
error code. Also add an unregistration API that takes the clk_hw
structure that was passed to the registration API. This way
provider drivers never have to deal with a struct clk pointer
unless they're using the clk consumer APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 16:51:58 -07:00
Stephen Boyd
a14b9e0512 clkdev: Remove clk_register_clkdevs()
Now that we've converted the only caller over to another clkdev
API, remove this one.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 16:51:58 -07:00
Heiko Stuebner
2b4e628648 clk: rockchip: drop unnecessary header comment
The internal clk header did contain a comment indicating that some of the
defined registers were shared over multiple clock controller variants.
In recent times, it was simply extended all the time and stopped providing
any meaningful information, so drop it and it's overlong line.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-19 21:17:55 +02:00
Heiko Stuebner
995d3fdeb2 clk: rockchip: reign in some overly long lines in the rk3399 controller
We allow overlong lines in the array portitions describing the clock
trees to ease readability by having each element always at the same
position. But the rest of the code should honor the 80 char limit.

Fix the newly added rk3399 clock code to respect that.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-19 21:07:01 +02:00
Heiko Stuebner
bdb4da8619 Merge branch 'v4.7-shared/clkids' into v4.7-clk/next 2016-04-16 03:04:15 +02:00
Heiko Stuebner
6111413be8 clk: rockchip: fix checkpatch errors in rk3399 dt-binding header
Some "please, no space before tabs" checkpatch warnings slipped through
the recent addition of the rk3399 dt-binding header, so fix them.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-16 03:03:58 +02:00
Grygorii Strashko
d5630b7a55 clk: ti: dra7: fix kernel boot with arg 'clocksource=gp_timer'
The OMAP Platform code provides possibility to select GP Timer as
default clocksource instead of counter_32K by using bootcmd parameter
'clocksource', but the system will crash during early boot when this
option is used on dra7 or omap5 platforms, because it will hit BUG()
statement:

 omap2_gptimer_clocksource_init
  ->BUG_ON(res);

This happens because clk_dev alias "sys_clkin_ck" is not registered.
Hence, fix it by adding missing "sys_clkin_ck" clk_dev aliases
definitions for omap5 and dra7.

Acked-by: Tero Kristo <t-kristo@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-15 17:30:07 -07:00
Tero Kristo
3db5ca27c8 clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
max-rate parameter based on the DPLL types.

[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-15 17:26:51 -07:00
Tero Kristo
c5cc2a0bc9 clk: ti: dpll: add support for specifying max rate for DPLLs
DPLLs typically have a maximum rate they can support, and this varies
from DPLL to DPLL. Add support of the maximum rate value to the DPLL
data struct, and also add check for this in the DPLL round_rate function.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-15 17:26:18 -07:00
Marc Gonzalez
fefe0535b7 clk: tango4: improve clkgen driver
Add support for USB and SDIO clocks.
Report unsupported setups and panic.

Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-15 17:16:06 -07:00
Vladimir Zapolskiy
cb0ceaf77d clk: at91: fix check of clk_register() returned value
The clk_register() function returns a valid pointer to struct clk or
ERR_PTR() error code, this makes a check for returned NULL value
useless and may lead to oops on error path.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: bcc5fd49a0 ("clk: at91: add a driver for the h32mx clock")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-15 16:57:09 -07:00
Stephen Boyd
d31d56ec17 clk: xgene: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Cc: Loc Ho <lho@apm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-15 16:50:27 -07:00
Stephen Boyd
4c211eaad6 clk: wm831x: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-15 16:50:23 -07:00
Stephen Boyd
d4da52c38c clk: twl6040: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-15 16:50:21 -07:00
Stephen Boyd
7ecf47c2c2 clk: rk808: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Cc: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-15 16:50:18 -07:00