Commit Graph

2522 Commits

Author SHA1 Message Date
Jason Gunthorpe
951f033d96 pinctrl: zynq: Add a 8 bit wide nand option
The hardware supports a 16 and 8 bit wide NAND bus, let users pick
either.

Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-04 15:19:00 +01:00
Boris BREZILLON
96bb12dead pinctrl: at91: add support for OUTPUT config
Add support for pin output control through the pinctrl config:
 - support enabling/disabling output on a given pin
 - support output level setting (high or low)

Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-31 09:16:46 +01:00
Maxime Ripard
e11dee2e98 pinctrl: sunxi: Deal with configless pins
Even though the our binding had the assumption that the allwinner,pull and
allwinner,drive properties were optional, the code never took that into
account.

Fix that.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-29 11:08:24 +02:00
Andy Shevchenko
b9aa65ba8e pinctrl: intel: merrifield: Add pin config group handlers
Pin config get() and set() handlers for pin groups were previously not
implemented by this driver. The pin_config_group_set() is particularly useful
for applying a common config setting to all pins in a specified group with a
single call, without the caller needing to reference each individual pin by
name.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-29 10:33:47 +02:00
Laxman Dewangan
e06c2ee5f1 pinctrl: generic: Parse pinmux init nodes if node status is okay
During pinmux registration, pinmux table is parsed from DT
for making the pinmux table configuration of pins.

Parse the only those node whose status is not disabled.
This will help on reusing the pin configuration table across
platform and disabling the node by status property if that node
is not needed on given platform.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-29 10:31:58 +02:00
Arnd Bergmann
24d6a91c9d pinctrl: max77620: add OF dependency
Drivers using pinconf_generic_params tables cannot be built with
CONFIG_OF disabled:

drivers/pinctrl/pinctrl-max77620.c:53:44: error: array type has incomplete element type ‘struct pinconf_generic_params’
drivers/pinctrl/pinctrl-max77620.c:55:3: error: field name not in record or union initializer
drivers/pinctrl/pinctrl-max77620.c:55:3: note: (near initialization for ‘max77620_cfg_params’)
drivers/pinctrl/pinctrl-max77620.c:56:3: error: field name not in record or union initializer

This adds a dependency for max77620 to disallow that configuration.

Alternatively, we could rework the pinctrl infrastructure to make the
configuration valid for compile-testing.

Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Lee Jones <lee.jones@linaro.org>
Fixes: 453943dc8f45 ("mfd: Enable compile testing for max77620 and max77686")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-29 10:30:16 +02:00
Tony Lindgren
cd23604a4b pinctrl: single: Drop pointless macro
This is left over from initial experiments with more properties.
It's only used in one place, so let's just get rid of it to make
the code more readable.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-28 13:54:00 +02:00
Tony Lindgren
223decc457 pinctrl: single: Drop custom names
>From tony Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Tue, 25 Oct 2016 08:33:34 -0700
Subject: [PATCHv2] pinctrl: single: Drop custom names

We no longer need to allocate custom names as those are dynamically
generated in pinctrl_register_one_pin() if no name is passed to
pinctrl_register_pins().

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-28 13:31:50 +02:00
Linus Walleij
ecdd1b890d Merge branch 'ib-sx150x' into devel 2016-10-24 16:30:55 +02:00
Neil Armstrong
9e80f9064e pinctrl: Add SX150X GPIO Extender Pinctrl Driver
Since the I2C sx150x GPIO expander driver uses platform_data to manage
the pins configurations, rewrite the driver as a pinctrl driver using
pinconf to get/set pin configurations from DT or debugfs.

The pinctrl driver is functionnally equivalent as the gpio-only driver
and can use DT for pinconf. The platform_data confirmation is dropped.

This patchset removed the gpio-only driver and selects the Pinctrl driver
config instead. This patchset also migrates the gpio dt-bindings to pinctrl
and add the pinctrl optional properties.

The driver was tested with a SX1509 device on a BeagleBone black with
interrupt support and on an X86_64 machine over an I2C to USB converter.

This is a fixed version that builds and runs on non-OF platforms and on
arm based OF. The GPIO version is removed and the bindings are also moved
to the pinctrl bindings.

Changes since v2
 - rebased on v4.9-rc1
 - removed MODULE_DEVICE_TABLE as in upstream bb411e771b
   ("gpio: sx150x: fix implicit assumption module.h is present")

Changes since v1
 - Fix Kconfig descriptions on pinctrl and gpio
 - Fix Kconfig dependency
 - Remove oscio support for non-789 devices
 - correct typo in dt bindings
 - remove probe reset for non-789 devices

Changes since RFC
 - Put #ifdef CONFIG_OF/CONFIG_OF_GPIO to remove OF code for non-of platforms
 - No more rely on OF_GPIO config
 - Moved and enhanced bindings to pinctrl bindings
 - Removed gpio-sx150x.c
 - Temporary select PINCTRL_SX150X when GPIO_SX150X
 - Temporary mark GPIO_SX150X as deprecated

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Peter Rosin <peda@axentia.se>
Acked-by: Rob Herring <robh@kernel.org>
ested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-24 16:30:40 +02:00
Maxime Ripard
cefbf1a1b2 pinctrl: sunxi: Support generic binding
Our bindings are mostly irrelevant now that we have generic pinctrl
bindings that cover exactly the same uses cases.

Add support for the new ones, and obviously keep our old binding support in
order to keep the ABI stable.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-24 16:30:14 +02:00
Neil Armstrong
4b0c0c25fa pinctrl: oxnas: Add support for OX820
Add support for the Oxford Semiconductor OX820 which is similar as OX810 but
has 50 pins and two registers banks to setup alternate functions.
Add specific pins, groups and functions structures.
Add DT match data to select corresponding support.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-24 16:30:14 +02:00
Neil Armstrong
93f889b965 pinctrl: oxnas: Move OX810SE specific function and structure as separate
Add refactoring to move ox810se specific functions into specific ops structures
an add support for the dt match data to get soc specific structures.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-24 16:30:14 +02:00
Maxime Ripard
07fe64ba21 pinctrl: sunxi: Handle bias disable
So far, putting NO_PULL in allwinner,pull was ignored, behaving like if
that property was not there at all.

Obviously, this is not the right thing to do, and in that case, we really
need to just disable the bias.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-24 16:30:14 +02:00
Maxime Ripard
42676fa4aa pinctrl: sunxi: Use macros from bindings header file for DT parsing
Since we have some bindings header for our hardcoded flags, let's use them
when we can.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-24 16:30:14 +02:00
Maxime Ripard
f233dbca62 pinctrl: sunxi: Rework the pin config building code
In order to support more easily the generic pinctrl properties, rework the
pinctrl maps configuration and split it into several sub-functions.

One of the side-effects from that rework is that we only parse the pin
configuration once, since it's going to be common to every pin, instead of
having to parsing once for each pin.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-24 16:30:14 +02:00
Mika Westerberg
c538b94367 pinctrl: intel: Only restore pins that are used by the driver
Dell XPS 13 (and maybe some others) uses a GPIO (CPU_GP_1) during suspend
to explicitly disable USB touchscreen interrupt. This is done to prevent
situation where the lid is closed the touchscreen is left functional.

The pinctrl driver (wrongly) assumes it owns all pins which are owned by
host and not locked down. It is perfectly fine for BIOS to use those pins
as it is also considered as host in this context.

What happens is that when the lid of Dell XPS 13 is closed, the BIOS
configures CPU_GP_1 low disabling the touchscreen interrupt. During resume
we restore all host owned pins to the known state which includes CPU_GP_1
and this overwrites what the BIOS has programmed there causing the
touchscreen to fail as no interrupts are reaching the CPU anymore.

Fix this by restoring only those pins we know are explicitly requested by
the kernel one way or other.

Cc: stable@vger.kernel.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=176361
Reported-by: AceLan Kao <acelan.kao@canonical.com>
Tested-by: AceLan Kao <acelan.kao@canonical.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-18 14:38:16 +02:00
Ville Syrjälä
a171bc51fa pinctrl: baytrail: Fix lockdep
Initialize the spinlock before using it.

INFO: trying to register non-static key.
the code is fine but needs lockdep annotation.
turning off the locking correctness validator.
CPU: 2 PID: 1 Comm: swapper/0 Not tainted 4.8.0-dwc-bisect 
Hardware name: Intel Corp. VALLEYVIEW C0 PLATFORM/BYT-T FFD8, BIOS BLAKFF81.X64.0088.R10.1403240443 FFD8_X64_R_2014_13_1_00 03/24/2014
 0000000000000000 ffff8800788ff770 ffffffff8133d597 0000000000000000
 0000000000000000 ffff8800788ff7e0 ffffffff810cfb9e 0000000000000002
 ffff8800788ff7d0 ffffffff8205b600 0000000000000002 ffff8800788ff7f0
Call Trace:
 [<ffffffff8133d597>] dump_stack+0x67/0x90
 [<ffffffff810cfb9e>] register_lock_class+0x52e/0x540
 [<ffffffff810d2081>] __lock_acquire+0x81/0x16b0
 [<ffffffff810cede1>] ? save_trace+0x41/0xd0
 [<ffffffff810d33b2>] ? __lock_acquire+0x13b2/0x16b0
 [<ffffffff810cf05a>] ? __lock_is_held+0x4a/0x70
 [<ffffffff810d3b1a>] lock_acquire+0xba/0x220
 [<ffffffff8136f1fe>] ? byt_gpio_get_direction+0x3e/0x80
 [<ffffffff81631567>] _raw_spin_lock_irqsave+0x47/0x60
 [<ffffffff8136f1fe>] ? byt_gpio_get_direction+0x3e/0x80
 [<ffffffff8136f1fe>] byt_gpio_get_direction+0x3e/0x80
 [<ffffffff813740a9>] gpiochip_add_data+0x319/0x7d0
 [<ffffffff81631723>] ? _raw_spin_unlock_irqrestore+0x43/0x70
 [<ffffffff8136fe3b>] byt_pinctrl_probe+0x2fb/0x620
 [<ffffffff8142fb0c>] platform_drv_probe+0x3c/0xa0
...

Based on the diff it looks like the problem was introduced in
commit 71e6ca61e8 ("pinctrl: baytrail: Register pin control handling")
but I wasn't able to verify that empirically as the parent commit
just oopsed when I tried to boot it.

Cc: Cristina Ciocan <cristina.ciocan@intel.com>
Cc: stable@vger.kernel.org
Fixes: 71e6ca61e8 ("pinctrl: baytrail: Register pin control handling")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-18 14:36:13 +02:00
Andrew Jeffery
8eb37aff76 pinctrl: aspeed-g5: Fix pin association of SPI1 function
The SPI1 function was associated with the wrong pins: The functions that
those pins provide is either an SPI debug or passthrough function
coupled to SPI1. Make the SPI1 mux function configure the relevant pins
and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins
that were already defined.

The notation used in the datasheet's multi-function pin table for the SoC is
often creative: in this case the SYS* signals are enabled by a single bit,
which is nothing unusual on its own, but in this case the bit was also
participating in a multi-bit bitfield and therefore represented multiple
functions. This fact was overlooked in the original patch.

Fixes: 56e57cb6c0 (pinctrl: Add pinctrl-aspeed-g5 driver)
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-18 14:36:12 +02:00
Andrew Jeffery
d3dbabe984 pinctrl: aspeed-g5: Fix GPIOE1 typo
This prevented C20 from successfully being muxed as GPIO.

Fixes: 56e57cb6c0 (pinctrl: Add pinctrl-aspeed-g5 driver)
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-18 14:36:11 +02:00
Andrew Jeffery
97e8c3f5e7 pinctrl: aspeed-g5: Fix names of GPID2 pins
Fixes simple typos in the initial commit. There is no behavioural
change.

Fixes: 56e57cb6c0 (pinctrl: Add pinctrl-aspeed-g5 driver)
Reported-by: Xo Wang <xow@google.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-18 14:36:11 +02:00
Andrew Jeffery
5366f1460c pinctrl: aspeed: "Not enabled" is a significant mux state
Consider a scenario with one pin P that has two signals A and B, where A
is defined to be higher priority than B: That is, if the mux IP is in a
state that would consider both A and B to be active on P, then A will be
the active signal.

To instead configure B as the active signal we must configure the mux so
that A is inactive. The mux state for signals can be described by
logical operations on one or more bits from one or more registers (a
"signal expression"), which in some cases leads to aliased mux states for
a particular signal. Further, signals described by multi-bit bitfields
often do not only need to record the states that would make them active
(the "enable" expressions), but also the states that makes them inactive
(the "disable" expressions). All of this combined leads to four possible
states for a signal:

         1. A signal is active with respect to an "enable" expression
         2. A signal is not active with respect to an "enable" expression
         3. A signal is inactive with respect to a "disable" expression
         4. A signal is not inactive with respect to a "disable" expression

In the case of P, if we are looking to activate B without explicitly
having configured A it's enough to consider A inactive if all of A's
"enable" signal expressions evaluate to "not active". If any evaluate to
"active" then the corresponding "disable" states must be applied so it
becomes inactive.

For example, on the AST2400 the pins composing GPIO bank H provide
signals ROMD8 through ROMD15 (high priority) and those for UART6 (low
priority). The mux states for ROMD8 through ROMD15 are aliased, i.e.
there are two mux states that result in the respective signals being
configured:

         A. SCU90[6]=1
         B. Strap[4,1:0]=100

Further, the second mux state is a 3-bit bitfield that explicitly
defines the enabled state but the disabled state is implicit, i.e. if
Strap[4,1:0] is not exactly "100" then ROMD8 through ROMD15 are not
considered active. This requires the mux function evaluation logic to
use approach 2. above, however the existing code was using approach 3.
The problem was brought to light on the Palmetto machines where the
strap register value is 0x120ce416, and prevented GPIO requests in bank
H from succeeding despite the hardware being in a position to allow
them.

Fixes: 318398c09a8d ("pinctrl: Add core pinctrl support for Aspeed SoCs")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-18 14:36:10 +02:00
Linus Torvalds
6afd563d4b ARM: SoC driver updates for v4.9
Driver updates for ARM SoCs, including a couple of newly added drivers:
 
 - The Qualcomm external bus interface 2 (EBI2), used in some of their
   mobile phone chips for connecting flash memory, LCD displays or
   other peripherals
 
 - Secure monitor firmware for Amlogic SoCs, and an NVMEM driver for the
   EFUSE based on that firmware interface.
 
 - Perf support for the AppliedMicro X-Gene performance monitor unit
 
 - Reset driver for STMicroelectronics STM32
 
 - Reset driver for SocioNext UniPhier SoCs
 
 Aside from these, there are minor updates to SoC-specific bus,
 clocksource, firmware, pinctrl, reset, rtc and pmic drivers.
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "Driver updates for ARM SoCs, including a couple of newly added
  drivers:

   - The Qualcomm external bus interface 2 (EBI2), used in some of their
     mobile phone chips for connecting flash memory, LCD displays or
     other peripherals

   - Secure monitor firmware for Amlogic SoCs, and an NVMEM driver for
     the EFUSE based on that firmware interface.

   - Perf support for the AppliedMicro X-Gene performance monitor unit

   - Reset driver for STMicroelectronics STM32

   - Reset driver for SocioNext UniPhier SoCs

  Aside from these, there are minor updates to SoC-specific bus,
  clocksource, firmware, pinctrl, reset, rtc and pmic drivers"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits)
  bus: qcom-ebi2: depend on HAS_IOMEM
  pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181
  clk: mvebu: Add clk support for the orion5x SoC mv88f5181
  dt-bindings: EXYNOS: Add Exynos5433 PMU compatible
  clocksource: exynos_mct: Add the support for ARM64
  perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver
  Documentation: Add documentation for APM X-Gene SoC PMU DTS binding
  MAINTAINERS: Add entry for APM X-Gene SoC PMU driver
  bus: qcom: add EBI2 driver
  bus: qcom: add EBI2 device tree bindings
  rtc: rtc-pm8xxx: Add support for pm8018 rtc
  nvmem: amlogic: Add Amlogic Meson EFUSE driver
  firmware: Amlogic: Add secure monitor driver
  soc: qcom: smd: Reset rx tail rather than tx
  memory: atmel-sdramc: fix a possible NULL dereference
  reset: hi6220: allow to compile test driver on other architectures
  reset: zynq: add driver Kconfig option
  reset: sunxi: add driver Kconfig option
  reset: stm32: add driver Kconfig option
  reset: socfpga: add driver Kconfig option
  ...
2016-10-07 21:23:40 -07:00
Linus Torvalds
6a497e9d58 This is the bulk of GPIO changes for the v4.9 series:
Subsystem improvements:
 
 - Do away with the last users of the obsolete Kconfig options
   ARCH_REQUIRE_GPIOLIB and ARCH_WANT_OPTIONAL_GPIOLIB (the latter
   always sounded like an item on a wishlist to Santa Claus to
   me). We can now select GPIOLIB and be done with it, for all
   archs. After some struggle it even work on UM. Not that it has
   GPIO, but if it wants to, it can select the library.
 
 - Continued efforts to make drivers properly either tristate or
   bool.
 
 - Introduce a warning for drivers assigning default triggers to
   their irqchip lines when probed from device tree, so we find and
   fix these ambigous drivers. It is agreed that in the OF config
   path, the device tree defines trigger characteristics.
 
 - The same warning, mutatis mutandis, for ACPI-probed GPIO
   irqchips.
 
 - We introduce the ability to mark certain IRQ lines as "unusable"
   as they can be taken by BIOS/firmware, unrouted in silicon and
   generally nasty if you use them, and such things. This is
   put to good use in the STMPE driver and also in the Cherryview
   pin control driver.
 
 - A new "mockup" virtual GPIO device that can be used for testing.
   The plan is to add unit tests under tools/* for exercising this
   device and verify that the kernel code paths are working as they
   should.
 
 - Make memory-mapped I/O-drivers depend on HAS_IOMEM. This was
   implicit all the time, but when people started building UM
   with allyesconfig or allmodconfig it exploded in their face.
 
 - Move some stray bits of device tree and ACPI HW description
   callbacks down into their respective implementation silo. These
   were causing issues when compiling on !HAS_IOMEM as well, so
   now eventually UM compiles the GPIOLIB library if it wants to.
 
 New drivers:
 
 - New driver for the Aspeed GPIO front-end companion to the
   pin controller merged through the pin control tree.
 
 - New driver for the LP873x PMIC GPIO portions.
 
 - New driver for Technologic Systems' I2C FPGA GPIO such as
   TS4900, TS-7970, TS-7990 and TS-4100.
 
 - New driver for the Broadcom BCM63xx series including BCM6338
   and BCM6345.
 
 - New driver for the Intel WhiskeyCove PMIC GPIO.
 
 - New driver for the Allwinner AXP209 PMIC GPIO portions.
 
 - New driver for Diamond Systems 48 line GPIO-MM, another of
   these port-mapped I/O expansion cards.
 
 - Support the STMicroelectronics STMPE1600 variant in the STMPE
   driver.
 
 Driver improvements:
 
 - The STMPE driver now supports rising/falling edge detection
   properly for IRQs.
 
 - The PCA954x will now fetch and enable its VCC regulator properly.
 
 - Major rework of the PCA953x driver with the goal of eventually
   switching it over to use regmap and thus modernize it even more.
 
 - Switch the IOP driver to use the generic MMIO GPIO library.
 
 - Move the ages old HTC EGPIO (extended GPIO) GPIO expander driver
   over to this subsystem from MFD, achieveing some separation of
   concerns.
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Merge tag 'gpio-v4.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull GPIO updates from Linus Walleij:
 "This is the bulk of GPIO changes for the v4.9 series:

  Subsystem improvements:

   - do away with the last users of the obsolete Kconfig options
     ARCH_REQUIRE_GPIOLIB and ARCH_WANT_OPTIONAL_GPIOLIB (the latter
     always sounded like an item on a wishlist to Santa Claus to me). We
     can now select GPIOLIB and be done with it, for all archs. After
     some struggle it even work on UM. Not that it has GPIO, but if it
     wants to, it can select the library.

   - continued efforts to make drivers properly either tristate or bool.

   - introduce a warning for drivers assigning default triggers to their
     irqchip lines when probed from device tree, so we find and fix
     these ambigous drivers. It is agreed that in the OF config path,
     the device tree defines trigger characteristics.

   - the same warning, mutatis mutandis, for ACPI-probed GPIO irqchips.

   - we introduce the ability to mark certain IRQ lines as "unusable" as
     they can be taken by BIOS/firmware, unrouted in silicon and
     generally nasty if you use them, and such things. This is put to
     good use in the STMPE driver and also in the Cherryview pin control
     driver.

   - a new "mockup" virtual GPIO device that can be used for testing.
     The plan is to add unit tests under tools/* for exercising this
     device and verify that the kernel code paths are working as they
     should.

   - make memory-mapped I/O-drivers depend on HAS_IOMEM. This was
     implicit all the time, but when people started building UM with
     allyesconfig or allmodconfig it exploded in their face.

   - move some stray bits of device tree and ACPI HW description
     callbacks down into their respective implementation silo. These
     were causing issues when compiling on !HAS_IOMEM as well, so now
     eventually UM compiles the GPIOLIB library if it wants to.

  New drivers:

   - new driver for the Aspeed GPIO front-end companion to the pin
     controller merged through the pin control tree.

   - new driver for the LP873x PMIC GPIO portions.

   - new driver for Technologic Systems' I2C FPGA GPIO such as TS4900,
     TS-7970, TS-7990 and TS-4100.

   - new driver for the Broadcom BCM63xx series including BCM6338 and
     BCM6345.

   - new driver for the Intel WhiskeyCove PMIC GPIO.

   - new driver for the Allwinner AXP209 PMIC GPIO portions.

   - new driver for Diamond Systems 48 line GPIO-MM, another of these
     port-mapped I/O expansion cards.

   - support the STMicroelectronics STMPE1600 variant in the STMPE
     driver.

  Driver improvements:

   - the STMPE driver now supports rising/falling edge detection
     properly for IRQs.

   - the PCA954x will now fetch and enable its VCC regulator properly.

   - major rework of the PCA953x driver with the goal of eventually
     switching it over to use regmap and thus modernize it even more.

   - switch the IOP driver to use the generic MMIO GPIO library.

   - move the ages old HTC EGPIO (extended GPIO) GPIO expander driver
     over to this subsystem from MFD, achieveing some separation of
     concerns"

* tag 'gpio-v4.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (81 commits)
  gpio: add missing static inline
  gpio: OF: localize some gpiochip init functions
  gpio: acpi: separation of concerns
  gpio: OF: separation of concerns
  gpio: make memory-mapped drivers depend on HAS_IOMEM
  gpio: stmpe: use BIT() macro
  gpio: stmpe: forbid unused lines to be mapped as IRQs
  mfd/gpio: Move HTC GPIO driver to GPIO subsystem
  gpio: MAINTAINERS: Add an entry for GPIO mockup driver
  gpio/mockup: add virtual gpio device
  gpio: Added zynq specific check for special pins on bank zero
  gpio: axp209: Implement get_direction
  gpio: aspeed: remove redundant return value check
  gpio: loongson1: remove redundant return value check
  ARM: omap2: fix missing include
  gpio: tc3589x: fix up complaints on unsigned
  gpio: tc3589x: add .get_direction() and small cleanup
  gpio: f7188x: use gpiochip_get_data instead of container_of
  gpio: tps65218: use devm_gpiochip_add_data() for gpio registration
  gpio: aspeed: fix return value check in aspeed_gpio_probe()
  ...
2016-10-05 11:49:09 -07:00
John Crispin
6bcf3f6339 pinctrl: qcom: fix masking of pinmux functions
The following commit introduced a regression by not properly masking the
calculated value.

Fixes: 47a01ee9a6 ("pinctrl: qcom: Clear all function selection bits")
Signed-off-by: John Crispin <john@phrozen.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-04 00:36:20 +02:00
Linus Walleij
031ba28a81 gpio: acpi: separation of concerns
The generic GPIO library directly implement code for acpi_find_gpio()
which is only used with CONFIG_ACPI. This was probably done because
OF did the same thing, but I removed that so remove this too.

Rename the internal acpi_find_gpio() in gpiolib-acpi.c to
acpi_populate_gpio_lookup() which seems to be more appropriate anyway
so as to avoid a namespace clash with the same function.

Make the stub return -ENOENT rather than -ENOSYS (as that is for
syscalls!).

For some reason the sunxi pin control driver was including the private
gpiolib header, it works just fine without it so remove that oneliner.

Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-10-03 23:38:10 +02:00
Linus Walleij
8d0a0ac0ab Merge branch 'fixes' into devel 2016-09-23 17:41:40 +02:00
Nilesh Bacchewar
01dabe91b1 pinctrl: intel: Configure GPIO chip IRQ as wakeup interrupts
On some Intel BXT platform, wake-up from suspend-to-idle on pressing
power-button is not working. Its noticed that gpio-keys driver marking the
second level IRQ/power-button as wake capable but Intel pintctrl
driver is missing to mark GPIO chip/controller IRQ which first level IRQ
as wake cable if its GPIO pin IRQ is wakeble. So, though the first level
IRQ gets generated on power-button press, since it is not marked as
wake capable resume/wake-up flow is not happening.
Intel pintctrl/GPIO driver need to mark GPIO chip/controller IRQ (first
level IRQ) as wake capable iff GPIO pin's IRQ (second level IRQ) is marked
as wake cable.

Changes in v2:
 - Add missing irq initialisation.

Signed-off-by: Nilesh Bacchewar <nilesh.bacchewar@intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 15:14:21 +02:00
Mika Westerberg
d1073418d9 pinctrl: cherryview: Convert to use devm_gpiochip_add_data()
This simplifies the error handling and allows us to drop the whole
chv_pinctrl_remove() function.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 14:59:42 +02:00
Mika Westerberg
47c950d102 pinctrl: cherryview: Do not add all southwest and north GPIOs to IRQ domain
It turns out that for north and southwest communities, they can only
generate GPIO interrupts for lower 8 interrupts (IntSel value). The upper
part (8-15) can only generate GPEs (General Purpose Events).

Now the reason why EC events such as pressing hotkeys does not work if we
mask all the interrupts is that in order to generate either interrupts or
GPEs the INTMASK register must have that particular interrupt unmasked. In
case of GPEs the CPU does not trigger normal interrupt (and thus the GPIO
driver does not see it) but instead it causes SCI (System Control
Interrupt) to be triggered with the GPE in question set.

To make this all work as expected we only add those GPIOs to the IRQ domain
that can actually generate interrupts (IntSel value 0-7) and skip others.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 14:57:33 +02:00
Linus Walleij
0565f49cfe Linux 4.8-rc6
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Merge tag 'v4.8-rc6' into devel

Linux 4.8-rc6
2016-09-23 14:57:16 +02:00
Arnd Bergmann
f5f8aaf98d mvebu drivers for 4.9 (part 1)
- Add pinctrl and clk support for the Orion5x SoC mv88f5181 variant
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Merge tag 'mvebu-drivers-4.9-1' of git://git.infradead.org/linux-mvebu into next/drivers

Pull "mvebu drivers for 4.9 (part 1)" from Gregory CLEMENT:

- Add pinctrl and clk support for the Orion5x SoC mv88f5181 variant

* tag 'mvebu-drivers-4.9-1' of git://git.infradead.org/linux-mvebu:
  pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181
  clk: mvebu: Add clk support for the orion5x SoC mv88f5181
2016-09-21 22:37:18 +02:00
Jamie Lentin
c336dc7dac pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181
As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
pinctrl level, so re-use the definitions for both.

[gregory.clement@free-electrons.com: fix commit title]
Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-09-21 11:49:18 +02:00
Linus Walleij
31ebe86d6e pinctrl: nomadik: don't default-flag IRQs as falling
There is no point in adding any default trigger for these
GPIO interrupts: the device tree should contain all trigger
information and the platforms using the driver boots
exclusively from device tree.

Also the boot log is nagging me to fix this:

[    0.771057] ------------[ cut here ]------------
[    0.775695] WARNING: CPU: 0 PID: 1 at
   ../drivers/gpio/gpiolib.c:1622 _gpiochip_irqchip_add+0x138/0x160
[    0.785034] /soc/gpio@8012e000: Ignoring 2 default trigger
(...)
[    0.942962] gpio 8012e000.gpio: at address e08f8000
(etc ad nauseam)

Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-19 11:01:33 +02:00
Peter Griffin
147e1468b2 pinctrl: st: Remove STiH415/6 SoC pinctrl driver support.
STiH415/6 SoC support is being removed from the kernel.
This patch updates the ST pinctrl driver and removes
references to these obsolete platforms. As some structures
referenced by STiH407 based configuration were shared with
STiH416 we update these names to match the remaining
supported platform.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Cc: <linus.walleij@linaro.org>
Cc: <linux-gpio@vger.kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-15 15:55:25 +02:00
Jerome Brunet
0ef823bee7 pinctrl: amlogic: gxbb: add i2c pins
Add EE domains pins for the i2c devices A,B,C

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-15 15:55:25 +02:00
Jerome Brunet
cd1e3b01c7 pinctrl: amlogic: gxbb: add nand pins
Add EE domains pins for the NAND flash controller.
Even tough we have no driver for the NAND flash controller yet, we need
to have these pins in pinctrl as the actual pin are shared with the spifc
controller. The bootloader on the S905-P200 setup pinmux for the NAND
controller so we need the kernel to properly deactivate this if necessary.

Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-15 14:14:51 +02:00
Arnd Bergmann
49cf2f29ac pinctrl: stm32: add IRQ_DOMAIN_HIERARCHY dependency
The newly added irqchip support for the stm32 pinctrl driver uses
hierarchical IRQ domains as provided by the NVIC primary irqchip.
This works great for any configuration that may be relevant on
stm32, but when doing compile-testing (randconfig), we can
enable it without NVIC or any other primary irqchip that
enables IRQ_DOMAIN_HIERARCHY:

drivers/pinctrl/stm32/pinctrl-stm32.c:212:13: error: 'irq_chip_eoi_parent' undeclared here (not in a function)
drivers/pinctrl/stm32/pinctrl-stm32.c:213:20: error: 'irq_chip_mask_parent' undeclared here (not in a function)
drivers/pinctrl/stm32/pinctrl-stm32.c:214:20: error: 'irq_chip_unmask_parent' undeclared here (not in a function)
drivers/pinctrl/stm32/pinctrl-stm32.c:215:20: error: 'irq_chip_set_type_parent' undeclared here (not in a function)

This adds a Kconfig dependency to limit compile-testing to
configurations that have IRQ_DOMAIN_HIERARCHY already enabled.
It's not obvious whether we should use 'depends on' or 'select'
here, I think either one works, with 'depends on' being more
intuitive, while 'select' would be less likely to cause dependency
loops.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 0eb9f68333 ("pinctrl: Add IRQ support to STM32 gpios")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-15 14:13:10 +02:00
Jerome Brunet
6812f19e17 pinctrl: amlogic: gxbb: add spi nor pins
Add EE domains pins for the SPI flash controller

Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-15 14:06:18 +02:00
Linus Walleij
3049d1343f pinctrl: sh-pfc: Updates for v4.9 (take three)
- Return pinconf with arguments in packed format,
   - MSIOF and QSPI pin groups on R-Car V2H,
   - Voltage switching for SDHI on R-Car M2-W, E2, and M3-W.
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Merge tag 'sh-pfc-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.9 (take three)

  - Return pinconf with arguments in packed format,
  - MSIOF and QSPI pin groups on R-Car V2H,
  - Voltage switching for SDHI on R-Car M2-W, E2, and M3-W.
2016-09-14 14:37:36 +02:00
Simon Horman
77fd4136e5 pinctrl: sh-pfc: r8a7794: Implement voltage switching for SDHI
All the SHDIs can operate with either 3.3V or 1.8V signals, depending
on negotiation with the card.

Based on work by Wolfram Sang for the r8a7790.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-14 09:26:54 +02:00
Simon Horman
0e1396f101 pinctrl: sh-pfc: r8a7791: Implement voltage switching for SDHI
All the SHDIs can operate with either 3.3V or 1.8V signals, depending
on negotiation with the card.

Based on work by Wolfram Sang for the r8a7790.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-14 09:26:49 +02:00
Simon Horman
9a6caa13f8 pinctrl: sh-pfc: Add PORT_GP_24 helper macro
This follows the style of existing PORT_GP_X macros and
will be used by a follow-up patch for the r8a7791 SoC.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-14 09:26:35 +02:00
Martin Blumenstingl
9b5fb0ca5d pinctrl: meson-gxbb: add the missing SDIO interrupt pin
This adds the SDIO interrupt pin which can be used by sd_emmc_a.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Suggested-by: Neil Armstrong <narmstrong@baylibre.com>

Fixes: 29885a6565 ("pinctrl: meson-gxbb: add the pins for the
SDIO/sd_emmc_a controller")
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-13 13:38:39 +02:00
Arnd Bergmann
5595603526 pinctrl: aspeed: fix regmap error handling
The newly added aspeed driver tries to check for a negative return
value from a pinctrl function, but stores the intermediate value in
a 'bool' variable, which cannot work:

drivers/pinctrl/aspeed/pinctrl-aspeed.c: In function 'aspeed_sig_expr_set':
drivers/pinctrl/aspeed/pinctrl-aspeed.c:192:11: error: comparison of constant '0' with boolean expression is always false [-Werror=bool-compare]

This slightly reworks the logic to use an explicit comparison with zero
before assigning to the temporary variable.

Reported-by: Colin King <colin.king@canonical.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-13 10:41:49 +02:00
Julia Lawall
03e9888f95 pinctrl: mediatek: constify gpio_chip structures
These structures are only used to copy into other structures, so declare
them as const.

The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };

@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;

@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p

@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
 struct gpio_chip i = { ... };
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-13 10:39:33 +02:00
Julia Lawall
d9048cdbc9 pinctrl: stm32: constify gpio_chip structures
These structures are only used to copy into other structures, so declare
them as const.

The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };

@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;

@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p

@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
 struct gpio_chip i = { ... };
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-13 10:37:37 +02:00
Agrawal, Nitesh-kumar
e084448b5d pinctrl/amd: switch to using a bool for level
The earlier patch can be simplified by using a bool
to indicate level trigger.

Reviewed-by: Pankaj Sen <Pankaj.Sen@amd.com>
Signed-off-by: Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com>
[Fixup to earlier manually applied patch]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-13 10:24:37 +02:00
Alexandre TORGUE
0eb9f68333 pinctrl: Add IRQ support to STM32 gpios
This patch adds IRQ support to STM32 gpios.

The EXTI controller has 16 lines dedicated to GPIOs.
EXTI line n can be connected to only line n of one of the GPIO ports, for
example EXTI0 can be connected to either PA0, or PB0, or PC0...
This port selection is done by specifying the port number into System
Config registers.

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-13 10:13:01 +02:00
Sylwester Nawrocki
b09eed7f81 pinctrl: samsung: Remove an always false dev->of_node test
samsung_pinctrl_probe() can be called only after matching
the driver by the compatible string so this already implies
a non null dev->of_node.  Remove the always false test
and related error trace. While at it drop another error log
in case of memory allocation failure - any errors are logged
by the memory subsystem.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-12 15:45:16 +02:00