Commit Graph

10044 Commits

Author SHA1 Message Date
Daniel Vetter
92907cbbef Linux 4.4-rc2
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Merge tag 'v4.4-rc2' into drm-intel-next-queued

Linux 4.4-rc2

Backmerge to get at

commit 1b0e3a049e
Author: Imre Deak <imre.deak@intel.com>
Date:   Thu Nov 5 23:04:11 2015 +0200

    drm/i915/skl: disable display side power well support for now

so that we can proplery re-eanble skl power wells in -next.

Conflicts are just adjacent lines changed, except for intel_fbdev.c
where we need to interleave the changs. Nothing nefarious.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2015-11-23 09:04:05 +01:00
Daniel Vetter
15fbfccfe9 drm/i915: Update DRIVER_DATE to 20151120
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-23 08:46:16 +01:00
Imre Deak
29bb94bb4d drm/i915: take a power domain reference while checking the HDMI live status
There are platforms that don't need the full GMBUS power domain (BXT)
while others do (PCH, VLV/CHV). For optimizing this we would need to add
a new power domain, but it's not clear how much we would benefit given
the short time we hold the reference. So for now let's keep things
simple.

v2:
- fix commit message, PCH won't take any redundant power resource after
this change (Ville)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[fix commit message in v2 (Imre)]
Link: http://patchwork.freedesktop.org/patch/msgid/1447959301-1263-2-git-send-email-imre.deak@intel.com
2015-11-20 11:48:57 +02:00
Imre Deak
69172f210e drm/i915: take a power domain ref only when needed during HDMI detect
Suggested by Ville.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447959301-1263-1-git-send-email-imre.deak@intel.com
2015-11-20 11:48:57 +02:00
Lukas Wunner
366e39b4d2 drm/i915: Tear down fbdev if initialization fails
Currently if intelfb_create() errors out, it unrefs the bo even though
the fb now owns that reference. (Spotted by Ville Syrjälä.) We should
unref the fb instead of the bo.

However the fb was not necessarily allocated by intelfb_create(),
it could be inherited from BIOS (the fb struct was then allocated by
dev_priv->display.get_initial_plane_config()) and be in active use by
a crtc. In this case we should call drm_framebuffer_remove() instead
of _unreference() to also disable the crtc.

Daniel Vetter suggested that "fbdev teardown code will take care of it.
The correct approach is probably to not unref anything at all".

But if fbdev initialization fails, the fbdev isn't torn down and
occupies memory even though it's unusable. Therefore clobber it in
intel_fbdev_initial_config(). (Currently we ignore a negative return
value there.) The idea is that if fbdev initialization fails, the driver
behaves as if CONFIG_DRM_FBDEV_EMULATION wasn't set. Should X11 manage
to start up without errors, it will at least be able to use the memory
that would otherwise be hogged by the unusable fbdev.

Also, log errors in intelfb_create().

Don't call async_synchronize_full() in intel_fbdev_fini() when called
from intel_fbdev_initial_config() to avoid deadlock.

v2: Instead of calling drm_framebuffer_unreference() (if fb was not
    inherited from BIOS), call intel_fbdev_fini().

v3: Rebase on e00bf69644 (drm/i915: Move the fbdev async_schedule()
    into intel_fbdev.c), call async_synchronize_full() conditionally
    instead of moving it into i915_driver_unload().

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Link: http://patchwork.freedesktop.org/patch/msgid/49ce5f0daead24b7598ec78591731046c333c18d.1447938059.git.lukas@wunner.de
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-19 17:52:38 +01:00
Arun Siluvery
fb1a21114f Revert "drm/i915: Initialize HWS page address after GPU reset"
This reverts commit 2e5356da37.

It is now redundant as it is already covered in below commit which introduced
the changes to reuse initialization of resources in resume/reset path.

commit e84fe80337
Author: Nick Hoath <nicholas.hoath@intel.com>
Date:   Fri Sep 11 12:53:46 2015 +0100

    drm/i915: Split alloc from init for lrc

lrc_setup_hardware_status_page() in the same function gen8_init_common_ring()
takes care of this.

Cc: Nick Hoath <nicholas.hoath@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447951664-9347-1-git-send-email-arun.siluvery@linux.intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-19 17:51:16 +01:00
Lukas Wunner
54632abe8c drm/i915: Fix oops caused by fbdev initialization failure
intelfb_create() is called once on driver initialization. If it fails,
ifbdev->helper.fbdev, ifbdev->fb or ifbdev->fb->obj may be NULL.

Further up in the call stack, intel_fbdev_initial_config() calls
intel_fbdev_fini() to tear down the ifbdev on failure. This calls
intel_fbdev_destroy() which dereferences ifbdev->fb. Fix the ensuing
oops.

Also check in these functions if ifbdev is not NULL to avoid oops:

i915_gem_framebuffer_info() is called on access to debugfs file
"i915_gem_framebuffer" and dereferences ifbdev, ifbdev->helper.fb
and ifbdev->helper.fb->obj.

intel_connector_add_to_fbdev() / intel_connector_remove_from_fbdev()
are called when registering / unregistering an mst connector and
dereference ifbdev.

v3: Drop additional null pointer checks in intel_fbdev_set_suspend(),
    intel_fbdev_output_poll_changed() and intel_fbdev_restore_mode()
    since they already check if ifbdev is not NULL, which is sufficient
    now that intel_fbdev_fini() is called on initialization failure.
    (Requested by Daniel Vetter <daniel.vetter@ffwll.ch>)

Signed-off-by: Lukas Wunner <lukas@wunner.de>
Link: http://patchwork.freedesktop.org/patch/msgid/d05f0edf121264a9d0adb8ca713fd8cc4ae068bf.1447938059.git.lukas@wunner.de
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-19 17:00:24 +01:00
Daniel Vetter
ce7f172856 drm/i915: Fix i915_ggtt_view_equal to handle rotation correctly
The rotated view depends upon the rotation paramters, but thus far we
didn't bother checking for those. This seems to have been an issue
ever since this was introduce in

commit fe14d5f4e5
Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date:   Wed Dec 10 17:27:58 2014 +0000

    drm/i915: Infrastructure for supporting different GGTT views per object

But userspace is allowed to reuse framebuffer backing storage with
different framebuffers with different pixel formats/stride/whatever.
And e.g. SNA indeed does this. Hence we must check for all the
paramters to match, not just that it's rotated.

v2: intel_plane_obj_offset also needs to construct the full view, to
avoid fallout since they don't fully match.

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1444834266-12689-3-git-send-email-daniel.vetter@ffwll.ch
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-19 16:42:06 +01:00
Daniel Vetter
a6d09186fa drm/i915: Stuff rotation params into view union
We don't need 2 separate unions.

Note that this was done intentinoally

Author: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Date:   Wed May 6 14:35:38 2015 +0300

    drm/i915: Add a partial GGTT view type

on Tvrtko's request, but without a clear justification. Rotated views
are also not checking for matching paramters in i915_ggtt_view_equal,
which seems like a bug. But this patch here doesn't change that.

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1444834266-12689-2-git-send-email-daniel.vetter@ffwll.ch
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-19 16:42:01 +01:00
Daniel Vetter
75c82a5362 drm/i915: Drop return value from intel_fill_fb_ggtt_view
It can't fail and there's even a WARN_ON suggesting that if it would,
it would be a disaster.

Correct this to make things less confusing.

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1444834266-12689-1-git-send-email-daniel.vetter@ffwll.ch
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-19 16:40:54 +01:00
Namrta Salonie
bf68dc9dce drm/i915 : Fix to remove unnecsessary checks in postclose function.
Found by static analysis tool.

Signed-off-by: Namrta Salonie <namrta.salonie@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-19 16:40:53 +01:00
Jani Nikula
7383123647 Revert "drm/i915: skip modeset if compatible for everyone."
This reverts

commit 6764e9f872
Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Date:   Thu Aug 27 15:44:06 2015 +0200

    drm/i915: skip modeset if compatible for everyone.

Bring back the i915.fastboot module parameter, disabled by default, due
to backlight regression on Chromebook Pixel 2015.

Apparently the firmware of the Chromebook in question enables the panel
but disables backlight to avoid a brief garbage scanout upon loading the
kernel/module. With fastboot, we leave the backlight untouched, in this
case disabled. The user would have to do a modeset (i.e. not just crank
up the brightness) to enable the backlight.

There is no clean fix readily available, so get back to the drawing
board by reverting.

[N.B. The reference below is for when the thread was included on public
lists, and some of the context had already been dropped by then.]

Reported-and-tested-by: Olof Johansson <olof@lixom.net>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
References: http://marc.info/?i=CAKMK7uES7xk05ki92oeX6gmvZWAh9f2vL7yz=6T+fGK9J3X7cQ@mail.gmail.com
Fixes: 6764e9f872 ("drm/i915: skip modeset if compatible for everyone.")
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447921590-3785-1-git-send-email-jani.nikula@intel.com
2015-11-19 10:38:09 +02:00
Imre Deak
b9fec1672c drm/i915: add MISSING_CASE to a few port/aux power domain helpers
MISSING_CASE() would have been useful to track down a recent problem in
intel_display_port_aux_power_domain(), so add it there and a few related
helpers. This was also suggested by Ville in his review of the latest
DMC/DC changes, we forgot to address that.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447855045-7109-2-git-send-email-imre.deak@intel.com
2015-11-18 21:46:34 +02:00
Imre Deak
651174a4a0 drm/i915/ddi: fix intel_display_port_aux_power_domain() after HDMI detect
Due to the current sharing of the DDI encoder between DP and HDMI
connectors we can run the DP detection after the HDMI detection has
already set the shared encoder's type. For now solve this keeping the
current behavior and running the detection in this case too. For a proper
solution Ville suggested to split the encoder into an HDMI and DP one, that
can be done as a follow-up.

This issue triggers the WARN in intel_display_port_aux_power_domain() and
was introduced in:
commit 25f78f58e5
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date:   Mon Nov 16 15:01:04 2015 +0100

    drm/i915: Clean up AUX power domain handling

CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447855045-7109-1-git-send-email-imre.deak@intel.com
2015-11-18 21:44:17 +02:00
Ander Conselvan de Oliveira
c555a81ddf drm/i915: Remove platform specific *_dp_detect() functions
Their logic is exactly the same: check if the digital port is connected
and then call intel_dp_detect_dpcd(). So just put that logic in their
only caller: intel_dp_detect().

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447859970-9546-2-git-send-email-ander.conselvan.de.oliveira@intel.com
2015-11-18 17:48:24 +02:00
Ander Conselvan de Oliveira
51676d0e30 drm/i915: Don't do edp panel detection in g4x_dp_detect()
That call was moved to intel_dp_detect() in

commit d410b56d74
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Tue Sep 2 20:03:59 2014 +0100

    drm/i915/dp: Refactor common eDP lid detection

but it seem to have been resurrected in the following commit, probably
due to a wrong merge conflict resolution.

commit 2a592bec50
Author: Dave Airlie <airlied@redhat.com>
Date:   Mon Sep 1 16:58:12 2014 +1000

    drm/i915: handle G45/GM45 pulse detection connected state.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447859970-9546-1-git-send-email-ander.conselvan.de.oliveira@intel.com
2015-11-18 17:47:03 +02:00
Rodrigo Vivi
81e4e0c95d drm/i915: Send TP1 TP2/3 even when panel claims no NO_TRAIN_ON_EXIT.
On the commit 3301d40921 ("drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic")'
we already had identified that DP_PSR_NO_TRAIN_ON_EXIT
doesn't mean we shouldn't send TPS patterns, however we start sending the
minimal TP1 as possible and no TP2.

For most of the panels this is ok, but we found a reported case where
this is not true and panel keeps frozen without updating the screen for a while.

We could just get this case after patch "PSR: Don't Skip aux handshake on
DP_PSR_NO_TRAIN_ON_EXIT." is applied since that one fix the
hard freeze on this kind of panels.

Reference: https://bugs.freedesktop.org/show_bug.cgi?id=91436#c19

Cc: Ivan Mitev <ivan.mitev@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-18 16:01:40 +01:00
Rodrigo Vivi
bebbeaca84 drm/i915: PSR: Don't Skip aux handshake on DP_PSR_NO_TRAIN_ON_EXIT.
Since the beginning there is a confusion on the meaning of this bit.

A previous patch had identified this already and fixed it partially:
'commit 3301d409 ("drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic")

DP_PSR_NO_TRAIN_ON_EXIT means the source doesn't need to do the
training, but it doesn't tell to avoid TP patterns or to skip
aux handshake.

This patch fixes the hard freeze reported.

Reference: https://bugs.freedesktop.org/show_bug.cgi?id=91436
Reference: https://bugs.freedesktop.org/show_bug.cgi?id=91437

Cc: Ivan Mitev <ivan.mitev@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-18 16:01:39 +01:00
Rodrigo Vivi
20bb97fe0e drm/i915: Reduce PSR re-activation time for VLV/CHV.
With 'commit 30886c5a ("drm/i915: VLV/CHV PSR: Increase wait delay
 time before active PSR.")' we fixed a blank screen when first
activation was happening immediately after PSR being enabled.
There we gave more time for idleness by increasing the delay
between re-activating sequences.

However, commit "drm/i915: Delay first PSR activation."
delay the first activation in a better way keeping a good PSR
residency. So, we can now reduce the delay on re-enable.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-18 16:01:39 +01:00
Rodrigo Vivi
d0ac896a47 drm/i915: Delay first PSR activation.
When debuging the frozen screen caused by HW tracking with low
power state I noticed that if we keep moving the mouse non stop
you will miss the screen updates for a while. At least
until we stop moving the mouse for a small time and move again.

The actual enabling should happen immediately after
Display Port enabling sequence finished with links trained and
everything enabled. However we face many issues when enabling PSR
right after a modeset.

On VLV/CHV we face blank screens on this scenario and on HSW+
we face a recoverable frozen screen, at least until next
exit-activate sequence.

Another workaround for the same issue here would be to increase
re-enable idle time from 100 to 500 as we did for VLV/CHV.
However this patch workaround this issue in a better
way since it doesn't reduce PSR residency and also
allow us to reduce the delay time between re-enables at least
on VLV/CHV.

This is also important to make the sysfs toggle working properly.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-18 16:01:39 +01:00
Ville Syrjälä
f0f59a00a1 drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.

This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.

The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.

As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
  lea    0x70024(%rdx,%rax,1),%r9d
  mov    $0x1,%edx
- movslq %r9d,%r9
- mov    %r9,%rsi
- mov    %r9,-0x58(%rbp)
- callq  *0xd8(%rbx)
+ mov    %r9d,%esi
+ mov    %r9d,-0x48(%rbp)
 callq  *0xd8(%rbx)

So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.

v2: i915_mmio_reg_{offset,equal,valid}() helpers added
    s/_REG/_MMIO/ in the register defines
    mo more switch statements left to worry about
    ring_emit stuff got sorted in a prep patch
    cmd parser, lrc context and w/a batch buildup also in prep patch
    vgpu stuff cleaned up and moved to a prep patch
    all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 15:39:11 +02:00
Maarten Lankhorst
00490c22b1 drm/i915: Consider SPLL as another shared pll, v2.
When diagnosing a unrelated bug for someone on irc, it would seem the hardware can
be brought up by the BIOS with the embedded displayport using the SPLL for spread spectrum.

Right now this is not handled well in i915, and it calculates the crtc needs to
be reprogrammed on the first modeset without SSC, but  the SPLL itself was kept
active. Fix this by exposing SPLL as a shared pll that will not be returned
by intel_get_shared_dpll; you have to know it exists to use it.

Changes since v1:
- Create a separate dpll_hw_state.spll for spll, and use
  separate pll functions for spll.

Tested-by: Emil Renner Berthing <kernel@esmil.dk>
Tested-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447681332-6318-1-git-send-email-maarten.lankhorst@linux.intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-11-18 15:08:31 +02:00
Ville Syrjälä
9bca5d0ca7 drm/i915: Add missing ')' to SKL_PS_ECC_STAT define
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-29-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2015-11-18 14:35:53 +02:00
Ville Syrjälä
0670c5a688 drm/i915: Add 'offset' to uncore funcs
Add 'u32 offset' to the uncore register access functions. For now
it's the same as 'reg', but once type safety gets added 'reg' will be
the type safe register variable and 'offset' the raw offset.

v2: s/uint32_t/u32/ (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446839236-20035-1-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2015-11-18 14:35:49 +02:00
Ville Syrjälä
8a74db7a86 drm/i915: Pull the vgpu uncore funcs apart from the rest of gen6+
I need to add a new variable into GEN6_{READ,WRITE}_HEADER, but the vgpu
won't need it, so let's avoid an unused variable warning by splitting
the vgpu stuff to use its own macros.

Cc: Eddie Dong <eddie.dong@intel.com>
Cc: Jike Song <jike.song@intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>
Cc: Yu Zhang <yu.c.zhang@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-26-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Zhiyuan Lv <zhiyuan.lv@intel.com>
2015-11-18 14:35:46 +02:00
Ville Syrjälä
ab75bb5d85 drm/i915: Turn vgpu pdps into an array
We'll want to avoid performing arithmetic with register offsets, so
instead calculating the vgpu PDP as pdp0_lo+offset, make the PDPs
into an array. This way we can simply loop through them.

Cc: Eddie Dong <eddie.dong@intel.com>
Cc: Jike Song <jike.song@intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>
Cc: Yu Zhang <yu.c.zhang@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-25-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Zhiyuan Lv <zhiyuan.lv@intel.com>
2015-11-18 14:35:42 +02:00
Ville Syrjälä
0d925ea023 drm/i915: Wrap context LRI init in a macro
We set up a load of LRIs in the logical ring context. Wrap that stuff
in a macro to avoid typos with position of each reg/value pair in the
context. This also makes it easier to make the register defines type
safe.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-24-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2015-11-18 14:35:39 +02:00
Ville Syrjälä
35dc3f97a6 drm/i915: Give names to more ring registers
The logical render context population has a bunch of raw ring register
offsets. Use the names we have for them, and in cases where we we don't,
give them names.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-23-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2015-11-18 14:35:36 +02:00
Ville Syrjälä
9244a81701 drm/i915: Wrap ASSIGN_CTX_{PDP,PM4L} in do {} while(0)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-22-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2015-11-18 14:35:32 +02:00
Ville Syrjälä
8f40db776a drm/i915: Add wa_ctx_emit_reg()
Add a helper for emitting register offsets (for LRI/SRM) into the w/a
batch buffer.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-21-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2015-11-18 14:35:28 +02:00
Ville Syrjälä
f92a916220 drm/i915: Add functions to emit register offsets to the ring
When register type safety happens, we can't just try to emit the
register itself to the ring. Instead we'll need to extract the
offset from it first. Add some convenience functions that will do
that.

v2: Convert MOCS setup too

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-20-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2015-11-18 14:35:24 +02:00
Ville Syrjälä
e597ef4045 drm/i915: Make the cmd parser 64bit regs explicit
Add defines for the upper halves of the registers used by the cmd
parser. Getting rid of the arithmetic with the register offset
will help in making registers type safe.

v2: s/_HI/_UDW/ (Chris)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1446839080-18732-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 14:35:20 +02:00
Ville Syrjälä
8697600b40 drm/i915: Make the high dword offset more explicit in i915_reg_read_ioctl
Store the upper dword of the register offset in the whitelist as well.
This would allow it to read register where the two halves aren't sitting
right next to each other, and it'll make it easier to make register
access type safe.

While at it change the register offsets to u32 from u64. Our register
space isn't quite that big, yet :)

v2: Use ldw/udw as the suffixes, and add a note about
    64bit wide split regs (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446839021-18599-1-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2015-11-18 14:35:16 +02:00
Ville Syrjälä
3613cf1d88 drm/i915: s/0x50/RING_PSMI_CTL/
Use the RING_PSMI_CTL define insted of hand rolling the register offset.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-17-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2015-11-18 14:35:13 +02:00
Ville Syrjälä
e6c4c76366 drm/i915: Parametrize MOCS registers
v2: Use for_each_ring() (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446725633-6419-1-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2015-11-18 14:35:10 +02:00
Ville Syrjälä
6fa1c5f1a7 drm/i915: Parametrize L3 error registers
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-15-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2015-11-18 14:35:06 +02:00
Ville Syrjälä
086f8e84a0 drm/i915: Prefix raw register defines with underscore
Most of our register defines follow the convention that if there's a
need for the raw register offset, that one has an underscore sa a
prefix. The define (possibly parametrized) without the underscore is
the one people should normally use, since it will take into account
all the parameters and other potential offsets that are needed.

Fix up the few stragglers that don't follow this convention.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-14-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2015-11-18 14:35:02 +02:00
Ville Syrjälä
b2e8c6cd09 drm/i915: Streamline gpio_mmio_base deduction
If we ignore the BXT situation, we can observe that the only variables
affecting gpio_mmio_base is IS_VALLEVIEW and HAS_GMCH_DISPLAY. The BXT
situation we can fit into the same pattern if we change gmbus_pins_bxt[]
to house the GMCH GPIO register offsets (like we do for all other
platfotms). So let's do that.

We could even simplify the VLV situation more by including the
display_mmio_offset in the GPIO register defines, but let's leave it be
for now.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-13-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-18 14:35:00 +02:00
Ville Syrjälä
78e0d2e347 drm/i915: Store DVO SRCDIM register offset under intel_dvo_device
Store the DVO SRCDIM register offset alongside the DVO control register
offset in intel_dvo_device. This gets rid of the switch statement whose
case values are the DVO control register offsets. Such a construct would
cause problems for register type safety.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-12-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2015-11-18 14:34:57 +02:00
Ville Syrjälä
2a5c08323d drm/i915: s/is_sdvob/enum port/
Replace the is_sdvob bool and some sdvo_reg checks with enum port. This
makes the SDVO code look more modern, and gets rid of explicit register
offset checks in the code which will hamper register type checking.

v2: Add assert_sdvo_port_valid() (Chris)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1446838199-3666-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 14:34:54 +02:00
Ville Syrjälä
c48b53054c drm/i915: s/PCH_DP_/PORT_/ in intel_trans_dp_port_sel() and move it next to its only user
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-9-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2015-11-18 14:34:51 +02:00
Rodrigo Vivi
6d8175da1f drm/i915: Rely on TEST_SINK_START instead of tracking Sink CRC state on dev_priv.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-18 11:24:27 +01:00
Rodrigo Vivi
7e38eeff6d drm/i915: Stop tracking last calculated Sink CRC.
It was created at 'commit aabc95dcf2 (drm/i915: Dont -ETIMEDOUT
on identical new and previous (count, crc).")' becase the counter
wasn't reliable.

Now that we properly wait for the counter to be reset we can rely
a bit more in the counter.

Also that patch stopped to return -ETIMEDOUT so the test case is
unable to skip when it is unreliable and end up in many fails
that should be skip instead.

So, with the counter more reliable we can remove
this hack that just makes things more confusing when test cases
are really expecting the same CRC and let test case skip if that's
not the case.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-18 11:23:55 +01:00
Rodrigo Vivi
c629784382 drm/i915: Make Sink crc calculation waiting for counter to reset.
According to VESA DP spec TEST_CRC_COUNT (Bits 3:0) at
TEST_SINK_MISC (00246h) is "Reset to 0 when TEST_SINK bit 0 = 0;

So let's give few vblanks so we are really sure that this counter
is really zeroed on the next sink_crc read.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-18 11:22:34 +01:00
Rodrigo Vivi
d72f9d919a drm/i915: Allow 1 vblank to let Sink CRC calculation to start or stop.
According to VESA DP Spec, setting TEST_SINK_START (bit 0)
of TEST_SINK (00270h) "Stop/Start calculating CRC on the next frame"

So let's wait at least 1 vblank to really say the calculation
stopped or started.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-18 11:21:50 +01:00
Mika Kuoppala
0f94592efd drm/i915: Fix gpu frequency change tracing
With gen < 9 we have had always 50Mhz units as our hw
ratio. With gen >= 9 the hw ratio changed to 16.667Mhz (50/3).
The result was that our gpu frequency tracing started to output
values 3 times larger than expected due to hardcoded scaling
value. Fix this by using  Use intel_gpu_freq() when generating Mhz
value from ratio for 'intel_gpu_freq_change' trace event.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92591
Cc: stable@vger.kernel.org # v4.3+
Reported-by: Eero Tamminen <eero.t.tamminen@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447776866-29384-1-git-send-email-mika.kuoppala@intel.com
2015-11-18 11:22:07 +02:00
Patrik Jakobsson
a03bc7cd63 drm/i915/skl: Remove unused suspend and resume callbacks
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447084107-8521-13-git-send-email-patrik.jakobsson@linux.intel.com
2015-11-17 20:55:21 +02:00
Patrik Jakobsson
443646c7ee drm/i915/gen9: Add boot parameter for disabling DC6
v2: Use _unsafe (Jani)
v3: Allow specifying specific DC-states instead of just DC6 (Imre)

Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447682467-6237-3-git-send-email-patrik.jakobsson@linux.intel.com
2015-11-17 20:55:20 +02:00
Patrik Jakobsson
9f836f9016 drm/i915/gen9: Turn DC handling into a power well
Handle DC off as a power well where enabling the power well will prevent
the DMC to enter selected DC states (required around modesets and Aux
A). Disabling the power well will allow DC states again. For now the
highest DC state is DC6 for Skylake and DC5 for Broxton but will be
configurable for Skylake in a later patch.

v2: Check both DC5 and DC6 bits in power well enabled function (Ville)
v3:
- Remove unneeded DC_OFF case in skl_set_power_well() (Imre)
- Add PW2 dependency to DC_OFF (Imre)
v4: Put DC_OFF before PW2 in BXT power well array

Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
[fixed line over 80 and parenthesis alignment checkpatch warns (imre)]
Link: http://patchwork.freedesktop.org/patch/msgid/1447687201-24759-1-git-send-email-patrik.jakobsson@linux.intel.com
2015-11-17 20:55:20 +02:00
Patrik Jakobsson
cd02ac52eb drm/i915: Explain usage of power well IDs vs bit groups
v2: Add explanation of the fixed power well bits (Imre)

Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447682467-6237-2-git-send-email-patrik.jakobsson@linux.intel.com
2015-11-17 20:55:20 +02:00