GPF1..5 banks in Exynos5433 are located in two pinctrl devices: ALIVE and
IMEM. Although they are partially located in ALIVE section, the state of
their registers in IMEM section is lost after suspend/resume cycle. To
properly handle such case, those banks have to be defined with standard
'exynos5433_bank_type_off' type (with PINCFG_TYPE_CON_PDN and
PINCFG_TYPE_PUD_PDN register offsets). This automatically instructs
the generic Samsung pinctrl suspend/resume code to save and restore state
of those registers.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
We already have macros for values used by driver and Device Tree
sources for pin mux configuration. Use them instead of duplicating
defines.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Exynos pinctrl drivers contain pretty big per-SoC data structures. The
pinctrl-exynos object file contained code and data for both ARMv7 and
ARMv8 SoCs thus it grew big. There will not be a shared image between
ARMv7 and ARMv8 so there is no need to combine all of this into one
driver.
Splitting the data allows to make it more granular (e.g. code related to
ARMv8 Exynos is self-contained), slightly speed up the compilation and
reduce the effective size of compiled kernel.
The common data structures and functions reside still in existing
pinctrl-exynos.c. Only the SoC-specific parts were moved out to new
files. Except marking few functions non-static and adding them to
header, there were no functional changes in the code.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
The pinctrl-exynos.h header is included only once so till now it did not
require an include guard. However adding such is harmless and makes
code prepared for more inclusions.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
The commit 1259feddd0f8("pinctrl: samsung: Fix the width of
PINCFG_TYPE_DRV bitfields for Exynos5433") already fixed
the different width of PINCFG_TYPE_DRV from previous Exynos SoC.
However wrong merge conflict resolution was chosen in commit
7f36f5d11c ("Merge tag 'v4.10-rc6' into devel") effectively dropping
the changes for PINCFG_TYPE_DRV. Re-do them here.
The macro EXYNOS_PIN_BANK_EINTW is no longer used so remove it.
Fixes: 7f36f5d11c ("Merge tag 'v4.10-rc6' into devel")
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch fixes the wrong width of PINCFG_TYPE_DRV bitfields for Exynos5433
because PINCFG_TYPE_DRV of Exynos5433 has 4bit fields in the *_DRV
registers. Usually, other Exynos have 2bit field for PINCFG_TYPE_DRV.
Fixes: 3c5ecc9ed3 ("pinctrl: exynos: Add support for Exynos5433")
Cc: stable@vger.kernel.org
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch supports the multiple IORESOURCE_MEM resources for one pin-bank.
In the pre-existing Exynos series, the registers of the gpio bank are included
in the one memory map. But, some gpio bank need to support the one more memory
map (IORESOURCE_MEM) because the registers of gpio bank are separated into
the different memory map.
For example,
The both ALIVE and IMEM domain have the different memory base address.
The GFP[1-5] of exynos5433 are composed as following:
- ALIVE domain : WEINT_* registers
- IMEM domain : CON/DAT/PUD/DRV/CONPDN/PUDPDN register
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: linux-gpio@vger.kernel.org
Suggested-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Exynos7 uses different offsets for wakeup interrupt configuration registers.
So a new irq_chip instance for Exynos7 wakeup interrupts is added. The irq_chip
selection is now based on the wakeup interrupt controller compatible string.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Group all pin control drivers of Samsung platform together in
a sub-directory for easy maintenance.
Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
