Commit Graph

12 Commits

Author SHA1 Message Date
Yong Zhang
d11584a044 SH: irq: Remove IRQF_DISABLED
Since commit [e58aa3d2: genirq: Run irq handlers with interrupts disabled],
We run all interrupt handlers with interrupts disabled
and we even check and yell when an interrupt handler
returns with interrupts enabled (see commit [b738a50a:
genirq: Warn when handler enables interrupts]).

So now this flag is a NOOP and can be removed.

Signed-off-by: Yong Zhang <yong.zhang0@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-10-28 14:39:28 +09:00
Paul Mundt
e7dc951eec sh: CPU hotplug support for SH-X3 SMP.
This wires up CPU hotplug for SH-X3 SMP CPUs. Presently only secondary
cores can be hotplugged given that the boot CPU has to contend with the
broadcast timer. When real local timers are implemented this restriction
can be lifted.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-04-26 19:09:57 +09:00
Paul Mundt
7acb59eb4b sh: Make sure all SH-X3 cores are populated in the present CPU map.
This iterates over the maximum number of CPUs we plan to support and
makes sure they're all set in the present CPU map.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-04-26 18:44:04 +09:00
Paul Mundt
3366e3585f sh: Move platform smp ops in to their own structure.
This cribs the MIPS plat_smp_ops approach for wrapping up the platform
ops. This will allow for mixing and matching different ops on the same
platform in the future.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-04-21 12:23:25 +09:00
Paul Mundt
fecf066c2d sh: Disable IRQ balancing for timer and IPI IRQs.
Make sure that the timer IRQs and IPIs aren't enabled for IRQ balancing.
IPIs are disabled as a result of being percpu while the timers simply
disable balancing outright.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-04-15 11:59:28 +09:00
Paul Mundt
f0cb77372c sh: Fix up the secondary CPU entry point for 32bit mode.
Presently the secondary CPU entry point is only aimed at 29bit phys mode,
causing it to point to a stray virtual address in 32bit mode. Fix it up
after consulting with our shiny new __in_29bit_mode().

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-01-15 15:13:48 +09:00
Paul Mundt
94eab0bb20 sh: Force boot CPU in to light sleep mode for SH-X3 SMP.
All of the secondary CPUs are forced in to light sleep mode, but we were
missing the same initialization for the boot CPU. This resulted in
inconsistent sleep modes depending on which CPU we were on, confusing the
idle loop when not polling.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-10-16 17:19:08 +09:00
Paul Mundt
fc6191dd30 sh: Fix up clockevents broadcasting.
This fixes up the clockevents broadcasting code as detailed in commit
ee348d5a1d ("[ARM] realview: fix broadcast
tick support"). This saves us from having to do strange ordering things
with the broadcast clockevent device, relying on the rating instead.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-08-19 18:00:03 +09:00
Rusty Russell
e09377bae4 cpumask: Use accessors for cpu_*_mask: sh
Use the accessors rather than frobbing bits directly (the new versions
are const).

Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Mike Travis <travis@sgi.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-06-14 18:24:16 +09:00
Paul Mundt
71f0bdcab6 sh: smp: shove a cpu_relax() in the plat_start_cpu() busy loop.
Without this, certain versions of GCC will happily optimize the entire
loop out.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-09-08 10:35:03 +09:00
Paul Mundt
c7936b9abc sh: smp: Hook in to the generic IPI handler for SH-X3 SMP.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-09-08 10:35:03 +09:00
Paul Mundt
1a442fe02d sh: Initial SH-X3 SMP support.
This adds basic support for SH-X3 SMP (4 CPUs).

More IPI and cache debugging is necessary, mostly interfacing the
d-cache coherency and the I-cache broadcast invalidates. Only for
testing at present!

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-09-21 19:16:05 +09:00