Commit Graph

32 Commits

Author SHA1 Message Date
Michal Simek
932bd0d8db arm64: zynqmp: Add fpd/lpd dmas
Wire fpd and lpd dma channels to zynqmp.dtsi.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-21 14:07:34 +02:00
Naga Sureshkumar Relli
2f9ed1999a arm64: zynqmp: Set status disabled in dtsi
Do not enable smmu via dtsi. Enable it in board file when needed.

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-21 14:07:34 +02:00
Michal Simek
27af3993f7 arm64: zynqmp: Add new uartps compatible string
Mainline kernel has r1p12 compatible string now. Use this new compatible
string and also append generic compatible string.
Keep in your mind that using this generic compatible string not all uart
features will be available.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
2017-08-21 14:07:33 +02:00
Edgar E. Iglesias
e199f2cc1e arm64: zynqmp: Correct IRQ nr for the SMMU
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-21 14:07:33 +02:00
Michal Simek
7fb7820c57 arm64: zynqmp: Add support for RTC
Add support for RTC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-21 14:07:32 +02:00
Bharat Kumar Gogada
4a6514d523 arm64: zynqmp: Adding prefetchable memory space to pcie node
Adding prefetchable memory space to pcie device tree node.
Shifting configuration space to 64-bit address space.
Removing pcie device tree node from amba as it requires size-cells=<2>
in order to access 64-bit address space.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-21 14:07:32 +02:00
Michal Simek
8c50b1e435 arm64: zynqmp: Add CCI-400 node
Add CCI-400 node to DTSI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-21 14:07:31 +02:00
Michal Simek
17e76f95a4 arm64: zynqmp: Add dcc console for zynqmp
Add debug console to dtsi to be able to enable it in
board dts file.
Keep in your mind that every core has separate dcc port in case you want
to run SMP kernel.
DCC is very helpful communication channel for debugging.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-21 14:07:31 +02:00
Shubhrajyoti Datta
e31b7bb8e2 arm64: zynqmp: Add operating points
Adding operating-points-v2 for zynqmp.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-21 14:07:30 +02:00
Stefan Krsmanovic
1e4e25c8ae arm64: zynqmp: Add idle state for ZynqMP
Added the idle-states node to describe zynqmp idle states. Only
cpu-sleep-0 idle state is added in this patch. References to the
idle-states node are added in all CPU nodes. Time values: entry/exit
latencies and min-residency, needs to be tuned. arm,psci-suspend-param
is selected to comply with PSCIv1.0 and Extended StateID format.

Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com>
Acked-by: Will Wong <willw@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-21 14:07:30 +02:00
Michal Simek
400e188fa8 arm64: zynqmp: Add references to cpu nodes
Add missing references to all cpu nodes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
2017-08-21 14:07:29 +02:00
Rob Herring
d15c56cad0 arm64: dts: xilinx: fix PCI bus dtc warnings
dtc recently added PCI bus checks. Fix these warnings.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-07-20 13:31:28 +02:00
Moritz Fischer
c415f9e830 ARM64: zynqmp: Fix i2c node's compatible string
The Zynq Ultrascale MP uses version 1.4 of the Cadence IP core
which fixes some silicon bugs that needed software workarounds
in Version 1.0 that was used on Zynq systems.

Signed-off-by: Moritz Fischer <mdf@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Sören Brinkmann <soren.brinkmann@xilinx.com>
Cc: Rob Herring <robh+dt@kernel.org>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-01-02 14:14:36 +01:00
Michal Simek
4ea2a6be95 ARM64: zynqmp: Fix W=1 dtc 1.4 warnings
The patch removes these warnings reported by dtc 1.4:
Warning (unit_address_vs_reg): Node /amba_apu has a reg or ranges
property, but no unit name
Warning (unit_address_vs_reg): Node /memory has a reg or ranges
property, but no unit name

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-01-02 14:14:30 +01:00
Arnd Bergmann
37179033fc Merge branch 'dt/irq-fix' into next/dt64
* dt/irq-fix:
  arm64: dts: Fix broken architected timer interrupt trigger

This resolves a non-obvious conflict between a bugfix from
v4.8 and a cleanup for the exynos7 platform.
2016-09-14 22:48:29 +02:00
Marc Zyngier
f2a89d3b2b arm64: dts: Fix broken architected timer interrupt trigger
The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).

A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.

The respective maintainers are of course welcome to prove me wrong.

While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).

Acked-by: Duc Dang <dhdang@apm.com>
Acked-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-09-14 22:47:22 +02:00
Punnaiah Choudary Kalluri
908c9e733b ARM64: zynqmp: Correct the watchdog timer interrupt number
Corrected the watchdog timer interrupt number.
Origin value was for CSUPMU watchdog.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-08-19 12:31:36 +02:00
Michal Simek
886e7ddda0 ARM64: zynqmp: Add missing interrupt-parent to PMU node
ZynqMP is not using global interrupt-parent setting that's why
it has to be listed in every node separately. PMU node missed it and
this patch is adding it.

Reported-by: John Linn <John.Linn@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-08-19 12:29:11 +02:00
Michal Simek
78b83b8cb3 ARM64: zynqmp: Add PCIe node
Add PCIe node with prefetchable memory which goes beyond 4GB.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-08-19 12:29:10 +02:00
Michal Simek
7393fd8691 ARM64: zynqmp: Use 64bit size cell format
Use 64bit size cell format instead of 32bit for memory
description. Change 64bit sizes also for all others IPs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-08-19 12:29:00 +02:00
Alexander Graf
e753dc0359 ARM64: zynqmp: Align gic ranges for 64k in device tree
The GIC ranges in the zynqmp device tree are only 4kb aligned. Since
commit 12e14066f we automatically deal with aliases GIC regions though,
so we can map them transparently into guests even on 64kb page size
systems.

This patch makes use of that features and sets GICC and GICV to 64kb
aligned and sized regions.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-08-19 12:27:20 +02:00
Michal Simek
5087bccb2f ARM64: zynqmp: Extract clock information from EP108
Extract clocks and put it specific file to help with platform
autogeneration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-02-25 14:01:03 +01:00
Michal Simek
72e5df437b ARM64: zynqmp: Keep gpio node alphabetically sorted
No functional change.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-02-25 14:00:50 +01:00
Soren Brinkmann
bdd5739008 ARM64: zynqmp: DT: Add interrupt-controller property to GPIO
GPIO can be used as interrupt-controller. Add the missing properties to
the GPIO node.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-14 09:48:20 +01:00
Michal Simek
f49310dc62 ARM64: zynqmp: Move SPI nodes to the right location
Keep nodes sorted.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-31 10:46:34 +02:00
Michal Simek
8fd7a775c5 ARM64: zynqmp: Move uart and ttcs to the right location
Sort nodes in DTSI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-31 10:46:31 +02:00
Michal Simek
22eda14afc ARM64: zynqmp: Add DWC3 usb support
Add usb nodes to DTSI and enable both of them on ep108.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-31 10:46:27 +02:00
Michal Simek
ff92e3614a ARM64: zynqmp: Add SMMU support
Add SMMU DT node to DTSI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-31 10:46:27 +02:00
Michal Simek
3a8691f530 ARM64: zynqmp: Add CANs node for platform
Also enable can0 for ep108.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-31 10:46:26 +02:00
Michal Simek
b72b44b617 ARM64: zynqmp: Use zynqmp specific compatible string for gpio
The patch:
"gpio: Added support to Zynq Ultrascale+ MPSoC"
(sha1: bdf7a4ae37)
added zynqmp specific features. This patch is switching the driver to
use the zynqmp compatible string.
Also enable the driver for ep108 platform.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-31 10:46:25 +02:00
Suneel Garapati
8fae442f88 devicetree: xilinx: zynqmp: add sata node
add sata node with sata fixed clock nodes in dtsi file.
enable sata in zynqmp-ep108.dts with broken-gen2.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-31 10:46:25 +02:00
Michal Simek
5d1b79d2b2 ARM64: Add new Xilinx ZynqMP SoC
Initial version of device tree for Xilinx ZynqMP SoC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-03-11 22:57:06 +01:00