Commit Graph

4 Commits

Author SHA1 Message Date
Chen-Yu Tsai
18c3b30083 drm/sun4i: Pass pointers for associated backend and tcon into crtc init
sun4i_crtc controls the backend and tcon hardware blocks of the display
pipeline.

Pass pointers to the underlying devices into the crtc init function,
instead of trying to fetch them from the drm_device structure. This
avoids the headache of trying to figure out which devices the crtc
is actually associated with.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-09 11:21:52 +01:00
Chen-Yu Tsai
3c64fb3747 drm/sun4i: Add backend and tcon pointers to sun4i_crtc
sun4i_crtc controls the backend and tcon hardware blocks of the display
pipeline. Instead of doing so through the master drm structure, leave
pointers to the corresponding backend and tcon in itself.

Also drop the drm_device pointer, since it is no longer needed.

The next step forward would be to pass the pointers in through
sun4i_crtc_init as parameters. This would make it easier to support
multiple display pipelines layer on.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-07 22:24:01 +01:00
Chen-Yu Tsai
b3f266e428 drm/sun4i: Move layers from sun4i_drv to sun4i_crtc
This patch moves the sun4i_layers_init call from sun4i_drv_bind to
sun4i_crtc_init, and the layers pointer from struct sun4i_drv to
struct sun4i_crtc.

The layers are bound to a specific crtc, and they are not directly
used once initiated. They are used through their included drm_plane
structures.

Moving the layers into the crtc facilitates binding them to the crtc
explicitly, by setting the corresponding bit in their .possible_crtcs
fields right after the crtc is initialized. This is done in a later
patch.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-07 22:18:23 +01:00
Maxime Ripard
9026e0d122 drm: Add Allwinner A10 Display Engine support
The Allwinner A10 and subsequent SoCs share the same display pipeline, with
variations in the number of controllers (1 or 2), or the presence or not of
some output (HDMI, TV, VGA) or not.

Add a driver with a limited set of features for now, and we will hopefully
support all of them eventually

Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-04-28 10:30:05 +02:00