PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration
(pin biasing, drive strength control), but not pin-muxing.
Allow to fill the mux value table with -1 for those pins; pins with
mux value -1 will be skipped in the pin-mux set function. The mux
value type should be changed from "unsigned" to "int" in order to
accommodate -1 as a special case.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input
signal gating for each pin. (While, existing ones only support it
per pin-group.) This commit updates the core part for that.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The core part of the UniPhier pinctrl driver needs to support a new
capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens
because pinctrl drivers include really SoC-specific stuff.
This commit intends to tidy up SoC-specific parameters of the existing
drivers before adding the new one. Having just one flag would be
better than adding a new struct member every time a new SoC-specific
capability comes up.
At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE.
This capability (I'd say rather quirk) was added for PH1-Pro4 and
PH1-Pro5 as requirement from a customer. For those SoCs, one pin-mux
setting is controlled by the combination of two separate registers; the
LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4).
Because it is impossible to update two separate registers atomically,
the LOAD_PINCTRL register should be set in order to make the pin-mux
settings really effective.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive
strength control. Drive strength of some pins are controlled by
3-bit width registers (8-level granularity).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive
strength control. Some of the configuration registers on it have
3-bit width.
The feature will be supported in the next commit, but a problem is
that macro names are getting longer and longer in the current naming
scheme.
Before moving forward, this commit renames macros as follows:
UNIPHIER_PIN_DRV_4_8 -> UNIPHIER_PIN_DRV_1BIT
UNIPHIER_PIN_DRV_8_12_16_20 -> UNIPHIER_PIN_DRV_2BIT
UNIPHIER_PIN_DRV_FIXED_4 -> UNIPHIER_PIN_DRV_FIXED4
UNIPHIER_PIN_DRV_FIXED_5 -> UNIPHIER_PIN_DRV_FIXED5
UNIPHIER_PIN_DRV_FIXED_8 -> UNIPHIER_PIN_DRV_FIXED8
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Currently, every SoC driver defines struct pinctrl_desc statically,
i.e. it consumes memory footprint even if it is not probed.
In multi-platform, many pinctrl drivers are linked (generally as
built-in objects), although only one of them is actually used.
So, it is reasonable to allocate memory dynamically where possible.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use devm_pinctrl_register() for pin control registration and remove
need of .remove callback.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The core support for the pinctrl drivers for all the UniPhier SoCs.
Changes in v2:
- drop vogus THIS_MODULE because this file is always built-in
- drop vogus "include <linux/module.h> because this file is
always built-in
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
