Commit Graph

40082 Commits

Author SHA1 Message Date
Tony Lindgren
774facda20 Merge branch '7xx-iosplit-plat' with omap-fixes 2009-11-10 18:10:34 -08:00
Linus Torvalds
79051db9ae Merge branch 'for-linus' of git://github.com/at91linux/linux-2.6-at91
* 'for-linus' of git://github.com/at91linux/linux-2.6-at91:
  at91: at91sam9g45 family: identify several chip versions
  avr32: add two new at91 to cpu.h definition
2009-11-03 11:15:25 -08:00
Nicolas Ferre
d8951adeba at91: at91sam9g45 family: identify several chip versions
cpu_is_xxx() macros are identifying generic at91sam9g45 chip. This patch adds
the capacity to differentiate Engineering Samples and final lots through the
inclusion of  at91_cpu_fully_identify() and the related chip IDs with chip
version field preserved.

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
2009-11-03 18:42:31 +01:00
Nicolas Ferre
2f5d46d2f6 avr32: add two new at91 to cpu.h definition
Somme common drivers will need those at91 cpu_is_xxx() definitions. As
at91sam9g10 and at91sam9g45 are on the way to linus' tree, here is the patch
that adds those chips to cpu.h in AVR32 architecture.

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2009-11-03 18:36:35 +01:00
Linus Torvalds
9ddfd92909 Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits)
  MIPS: O32: Fix ppoll
  MIPS: Oprofile: Rename cpu_type from godson2 to loongson2
  MIPS: Alchemy: Fix hang with high-frequency edge interrupts
  MIPS: TXx9: Fix spi-baseclk value
  MIPS: bcm63xx: Set the correct BCM3302 CPU name
  MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store
  MIPS: Avoid potential hazard on Context register
  MIPS: Octeon: Use lockless interrupt controller operations when possible.
  MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity
  MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache
  MIPS: SMTC: Avoid queing multiple reschedule IPIs
  MIPS: GCMP: Avoid accessing registers when they are not present
  MIPS: GIC: Random fixes and enhancements.
  MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start
  MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands
  MIPS: SPRAM: Clean up support code a little
  MIPS: 1004K: Enable SPRAM support.
  MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4
  MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.
  MIPS: MTI: Fix accesses to device registers on MIPS boards
  ...
2009-11-03 08:09:57 -08:00
Linus Torvalds
fcef24d38e Merge branch 'fixes-s3c-2632-rc5' of git://git.fluff.org/bjdooks/linux
* 'fixes-s3c-2632-rc5' of git://git.fluff.org/bjdooks/linux:
  ARM: S3C2410: Fix sparse warnings in arch/arm/mach-s3c2410/gpio.c
  ARM: S3C2440: mini2440: Fix spare warnings
  ARM: S3C24XX: Fix warnings in arch/arm/plat-s3c24xx/gpio.c
  ARM: S3C2440: mini2440: Fix missing CONFIG_S3C_DEV_USB_HOST
  ARM: S3C24XX: arch/arm/plat-s3c24xx: Move dereference after NULL test
  ARM: S3C: Fix adc function exports
  ARM: S3C2410: Fix link if CONFIG_S3C2410_IOTIMING is not set
  ARM: S3C24XX: Introduce S3C2442B CPU
  ARM: S3C24XX: Define a macro to avoid compilation error
  ARM: S3C: Add info for supporting circular DMA buffers
  ARM: S3C64XX: Set rate of crystal mux
  ARM: S3C64XX: Fix S3C64XX_CLKDIV0_ARM_MASK value
2009-11-03 07:46:05 -08:00
Linus Torvalds
333a07437c Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6:
  Revert "[IA64] fix percpu warnings"
  [IA64] fix percpu warnings
  [IA64] SMT friendly version of spin_unlock_wait()
  [IA64] use printk_once() unaligned.c/io_common.c
  [IA64] Require SAL 3.2 in order to do extended config space ops
  [IA64] unsigned cannot be less than 0 in sn_hwperf_ioctl()
  [IA64] Restore registers in the stack on INIT
  [IA64] Re-implement spinaphores using ticket lock concepts
  [IA64] Squeeze ticket locks back into 4 bytes.
2009-11-02 10:22:25 -08:00
Linus Torvalds
c35102c3e1 Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm:
  ARM: ensure initial page tables are setup for SMP systems
  ARM: 5776/1: Check compiler version and EABI support when adding ARM unwind support.
  ARM: 5774/1: Fix Realview ARM1176PB board reboot
  ARM: Fix errata 411920 workarounds
  ARM: Fix sparsemem with SPARSEMEM_EXTREME enabled
  ARM: Use GFP_DMA only for masks _less_ than 32-bit
  ARM: integrator: allow Integrator to be built with highmem
  ARM: Fix signal restart issues with NX and OABI compat
2009-11-02 09:53:19 -08:00
Linus Torvalds
efcd9e0b91 Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86: Make EFI RTC function depend on 32bit again
  x86-64: Fix register leak in 32-bit syscall audting
  x86: crash_dump: Fix non-pae kdump kernel memory accesses
  x86: Side-step lguest problem by only building cmpxchg8b_emu for pre-Pentium
  x86: Remove STACKPROTECTOR_ALL
2009-11-02 09:45:17 -08:00
Tony Luck
e8c93fc7b7 Revert "[IA64] fix percpu warnings"
This reverts commit b94b08081f.

genksyms currently cannot handle complicated types for exported
percpu variables.  Drop this patch for now as it prevents a
module from being loaded on sn2 systems:

 xpc: no symbol version for per_cpu____sn_cnodeid_to_nasid
 xpc: Unknown symbol per_cpu____sn_cnodeid_to_nasid

Signed-off-by: Tony Luck <tony.luck@intel.com>
2009-11-02 09:23:08 -08:00
Russell King
4b46d64165 ARM: ensure initial page tables are setup for SMP systems
Mapping the same memory using two different attributes (memory
type, shareability, cacheability) is unpredictable.  During boot,
we encounter a situation when we're updating the kernel's page
tables which can lead to dirty cache lines existing in the cache
which are subsequently missed.  This causes stack corruption,
and therefore a crash.

Therefore, ensure that the shared and cacheability settings
matches the configuration that will be used later; this together
with the restriction in early_cachepolicy() ensures that we won't
create a mismatch during boot.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-11-02 16:59:59 +00:00
Claudio Scordino
6603a4fd51 ARM: 5776/1: Check compiler version and EABI support when adding ARM unwind support.
ARM unwind is known to compile only with EABI and not-buggy compilers.
The problem is not the unwinding information but the -fno-frame-pointer
option added as a result of !CONFIG_FRAME_POINTER.  Now we check the
compiler and raise a #warning in case of wrong compiler.

Signed-off-by: Claudio Scordino <claudio@evidence.eu.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-11-02 16:59:45 +00:00
Arnaud Patard
049a31afe1 MIPS: O32: Fix ppoll
sys_ppoll syscall needs to use a compat handler on 64bit kernels with o32
user-space.

Signed-off-by: Arnaud Patard <apatard@mandriva.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:08 +01:00
Wu Zhangjin
55f4e1d4fe MIPS: Oprofile: Rename cpu_type from godson2 to loongson2
Unify the naming method between kernel and the user-space oprofile tool.
Because loongson is used instead of godson in most of the places, we agreed
to use loongson instead, which will simplify future maintenance.

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Acked-by: Robert Richter <robert.richter@amd.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:08 +01:00
Manuel Lauss
44f2c586a3 MIPS: Alchemy: Fix hang with high-frequency edge interrupts
The handle_edge_irq() flowhandler disables edge int sources which occur
too fast (i.e. another edge comes in before the irq handler function
had a chance to finish).  Currently, the mask_ack() callback does not
ack the edges in hardware, leading to an endless loop in the flowhandler
where it tries to shut up the irq source.

When I rewrote the alchemy IRQ code  I wrongly assumed the mask_ack()
callback was only used by the level flowhandler, hence it omitted the
(at the time pointless) edge acks.  Turned out I was wrong; so here
is a complete mask_ack implementation for Alchemy IC, which fixes
the above mentioned problem.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:08 +01:00
Atsushi Nemoto
fcc152f3bf MIPS: TXx9: Fix spi-baseclk value
TXx9 SPI bit rate is calculated by:
	fBR = fSPI / 2 / (n + 1)
	(fSPI is SPI master clock freq, i.e. imbusclk freq.)
So use imbus_clk / 2 as a spi-baseclk.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:07 +01:00
Florian Fainelli
2b5b9b786c MIPS: bcm63xx: Set the correct BCM3302 CPU name
For consistency with other BCM63xx SoC set the CPU name to "Broadcom
BCM6338" when actually running on that system.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:07 +01:00
Zhang Le
e8d4c342e5 MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store
Loongson 2 does not have dcache aliases when is using 16k pages. and the

And because Loongson 2 doesn't do SMP , cpu_icache_snoops_remote_store does
not matter here.

Signed-off-by: Zhang Le <r0bertz@gentoo.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:07 +01:00
Ralf Baechle
c2ea1d56ea MIPS: Avoid potential hazard on Context register
set_saved_sp reads Context register. Avoid reading stale value from
earlier incomplete write.

Issue found and fixed for head.S by Chris Dearman <chris@mips.com>.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:07 +01:00
David Daney
cd847b7857 MIPS: Octeon: Use lockless interrupt controller operations when possible.
Some newer Octeon chips have registers that allow lockless operation of
the interrupt controller.  Take advantage of them.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:07 +01:00
David Daney
b6b74d5490 MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity
Since the locks are used from interrupt context we need the
irqsave/irqrestore versions of the locking functions.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:07 +01:00
Ralf Baechle
0db2b74e91 MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:06 +01:00
Jaidev Patwardhan
2e41f91d9e MIPS: SMTC: Avoid queing multiple reschedule IPIs
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:06 +01:00
Jaidev Patwardhan
05cf20790b MIPS: GCMP: Avoid accessing registers when they are not present
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:06 +01:00
Chris Dearman
7098f74828 MIPS: GIC: Random fixes and enhancements.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:06 +01:00
Chris Dearman
2ee0a42961 MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start
Signed-off-by: Chris Dearman (chris@mips.com)
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:05 +01:00
Nigel Stephens
cea2be4443 MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands
This patch ensures that the sign bit is always updated for NaN operands.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:05 +01:00
Chris Dearman
a074f0e89f MIPS: SPRAM: Clean up support code a little
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:05 +01:00
Ralf Baechle
a4e7cac18f MIPS: 1004K: Enable SPRAM support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:04 +01:00
Ralf Baechle
a951f2829a MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4
Based on original patch by Chris Dearman <chris@mips.com>.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:04 +01:00
Ralf Baechle
c708875551 MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:04 +01:00
Chris Dearman
accfd35a4e MIPS: MTI: Fix accesses to device registers on MIPS boards
This fixes the remaining problems introduced by
f197465384 (incorrect access length &
byteswapping in bigendian mode)

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:04 +01:00
Kevin Cernekee
0f334a3e8c MIPS: Fix machine check exception in kmap_coherent()
On an SMP system with cache aliases, the following sequence of events may
happen:

1) copy_user_highpage() runs on CPU0, invoking kmap_coherent() to create a
   temporary mapping in the fixmap region
2) copy_page() starts on CPU0
3) CPU1 sends CPU0 an IPI asking CPU0 to run local_r4k_flush_cache_page()
4) CPU0 takes the interrupt, interrupting copy_page()
5) local_r4k_flush_cache_page() on CPU0 calls kmap_coherent() again
6) The second invocation of kmap_coherent() on CPU0 tries to use the
   same fixmap virtual address that was being used by copy_user_highpage()
7) CPU0 throws a machine check exception for the TLB address conflict

Fixed by creating an extra set of fixmap entries for use in interrupt
handlers.  This prevents fixmap VA conflicts between copy_user_highpage()
running in user context, and local_r4k_flush_cache_page() invoked from an
SMP IPI.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:04 +01:00
Ralf Baechle
39d2211d20 MIPS: MTX-1: Fix build if CONFIG_PCI is disabled.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:04 +01:00
Florian Fainelli
72838a1703 MIPS: AR7: register watchdog device only if enabled in hw configuration
This patch checks if the watchdog enable bit is set in the DCL register
meaning that the hardware watchdog actually works and if so, register the
ar7_wdt platform_device.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:03 +01:00
Florian Fainelli
2cfac7f7f2 MIPS: BCM63xx: Prepare for watchdog support
This patch prepares the board code to register a bcm63xx_wdt
platform_device that we are going to use in a subsequent patch.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:03 +01:00
Florian Fainelli
6c1e7a5ad9 MIPS: BCM63xx: Make bcm63xx_uart_register an initfunc
This patch removes the calls to bcm63xx_uart_register in board_bcm963xx.c
and make bcm63xx_uart_register an initfunc.  Allows us to remove
bcm63xx_dev_uart.h which was there to make checkpatch.pl happy.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:03 +01:00
Florian Fainelli
e85843a1e1 MIPS: AU1000: Fix build failure for db1x00 configured for Au1100 SoC
This patch fixes the following warning, which becomes an error due to
-Werror to be turned on:
  CC      arch/mips/alchemy/common/gpiolib-au1000.o
cc1: warnings being treated as errors
arch/mips/alchemy/common/gpiolib-au1000.c: In function 'au1100_gpio2_to_irq':
/home/florian/dev/kernel/linux-queue/arch/mips/include/asm/mach-au1x00/gpio-au1000.h:107: warning: control reaches end of non-void function

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:03 +01:00
Florian Fainelli
e85d59df13 MIPS: BCM63xx: Fix soft-reset lockup on BCM6345
This patch fixes a lockup on BCM6345 where setting the PLL soft reset bit
will also lock the other blocks including UART.  Instead of setting only
the PLL soft reset bit in the software reset register, set this bit but do
not touch the others.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:03 +01:00
Ralf Roesch
a2e62f3a85 MIPS: TXx9: Fix error handling / Fix for noenexisting gpio_remove.
Error was introduced by commit 0385d1f3d394c6814be0b165c153fc3fc254469a.

Signed-off-by: Ralf Roesch <ralf.roesch@rw-gmbh.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:02 +01:00
Wu Zhangjin
c49e38c1a5 MIPS: Add IRQF_TIMER flag for timer interrupts
As the commit 3ee4c147 shows, we need to "Add IRQF_TIMER flag for timer
interrupts", Atsushi Nemoto have reported that some other timer interrupts
should be considered, Here it is.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:02 +01:00
Wu Zhangjin
80b8585b07 MIPS: 64-bit: Fix o32 lookup_dcookie syscall
An o32 aplication passes a 64-bit value in a pair of registers; a 64-bit
kernel expects a 64-bit argument in a single register.

Signed-off-by: Chen Jie <chenj@lemote.com>
Signed-off-by: Hu Hongbing <huhb@lemote.com>
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:02 +01:00
Ralf Baechle
a22d621c80 MIPS: VPE: Remove stray unlock_kernel.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Reported-by: Josip Rodin <joy@entuzijast.net>
2009-11-02 12:00:02 +01:00
Wu Zhangjin
f45e518361 MIPS: Add IRQF_TIMER flag for timer interrupts
Along the lines of d6c585a434, add IRQF_TIMER
flag for all timer interrupts  This ensures that timer interrupts won't be
disabled on suspend and not threaded for PREEMPT_RT.

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:02 +01:00
Wu Zhangjin
b40bb20e74 MIPS: Loongson: Remove redundant local_irq_disable()
That code is executed with irq disabled already, so, remove the redundant
local_irq_disable() here.

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:02 +01:00
Ralf Baechle
01a6fbf759 MIPS: IP27: Fix build
Broken by 182a85f8a1.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:01 +01:00
Ralf Baechle
962a9dd47e MIPS: Cleanup CONFIG_DEBUG_STACK_USAGE version of alloc_thread_info.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:01 +01:00
David Daney
067f3290f7 MIPS: Octeon: Fix compile error in arch/mips/cavium-octeon/smp.c
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:01 +01:00
Ralf Baechle
d30cecbcbe MIPS: Don't write ones to reserved entryhi bits.
We've silently been relying on the hardware chopping off excess, reserved
ASID bits for no better reason that it saving an instruction.  Because we
already have:

#define cpu_asid(cpu, mm)       (cpu_context((cpu), (mm)) & ASID_MASK)

in <asm/mmu_context.h>.

We can use a cleanup to avoid writing non-zero bits into the reserved
entryhi bits.  This avoid triggering some debugging assertion in the
Cavium simulator.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:01 +01:00
Ralf Baechle
22242681cf MIPS: Extend COMMAND_LINE_SIZE
Some firmware may pass well over 256 bytes these days.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02 12:00:01 +01:00