Commit Graph

532 Commits

Author SHA1 Message Date
Sergei Shtylyov
c8bac70f07 pinctrl: sh-pfc: r8a7794: Add R8A7745 support
Renesas RZ/G1E (R8A7745) is pin compatible with R-Car E2 (R8A7794),
however it doesn't have several automotive specific peripherals.
Annotate all the items that only exist on the R-Car SoCs...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
[geert: Drop annotations, as they are implied by pin groups/functions]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-16 13:53:15 +02:00
Sergei Shtylyov
13385db547 pinctrl: sh-pfc: r8a7794: Remove reserved bits
The R8A7794 PFC driver was apparently based on the preliminary revisions
of the user's manual which had some signals and MOD_SEL register fields
described which the recent manual changed to reserved. Of course, these
signals haven't ever been really used, which makes removing them
painless.

While at it, make the large *enum* look better by starting a new line
each time a new row in the IPSR and MOD_SEL register field tables is
started.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-16 13:48:24 +02:00
Sergei Shtylyov
d24709f5d6 pinctrl: sh-pfc: r8a7794: Remove AVB_AVTP_* groups
The ATA_AVTP_* signals are documented as reserved in the recent R-Car E2
user's manual (the only remaining mention is in the table 5.2 and I believe
it's a simple overlook).  Remove the AVB_AVTP_* pinmux groups -- we will
remove the signals themselves in the next patch, along with the other now
reserved bits...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-16 13:48:23 +02:00
Sergei Shtylyov
5128238dd7 pinctrl: sh-pfc: r8a7794: Rename some I2C signals
The R8A7794 PFC driver was apparently based on the preliminary revisions
of the user's manual which called I2C5 device IIC0 and IIC0 device IIC1.
Luckily, these signals haven't been used for any functions/groups so
far, so the renaming should be painless..

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-16 13:48:23 +02:00
Sergei Shtylyov
8df6270149 pinctrl: sh-pfc: r8a7791: Add R8A7743 support
Renesas RZ/G1M (R8A7743) is pin compatible with R-Car M2-W/N (R8A7791/3),
however it doesn't have several automotive specific peripherals.  Annotate
all the items that only exist on the R-Car SoCs and only supply the pin
groups/functions existing on a given SoC...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
[geert: Drop annotations, as they are implied by pin groups/functions]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-16 13:45:28 +02:00
Kuninori Morimoto
5c6aa7bdd2 pinctrl: sh-pfc: r8a7795-es1: Rename SSI_{WS,SCK}34 to SSI_{WS,SCK}349
R-Car Gen3 is using SSI_{WS,SCK}349 instead of SSI_{WS,SCK}34.
But, current code is based on old datasheet which had typo.
This patch fixes this typo.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-16 11:53:51 +02:00
Kuninori Morimoto
68e6389200 pinctrl: sh-pfc: r8a7795: Rename SSI_{WS,SCK}34 to SSI_{WS,SCK}349
R-Car Gen3 is using SSI_{WS,SCK}349 instead of SSI_{WS,SCK}34.
But, current code is based on old datasheet which had typo.
This patch fixes this typo.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-16 11:53:45 +02:00
Kuninori Morimoto
60ffe393bb pinctrl: sh-pfc: r8a7796: Add Audio clock pin support
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-16 11:53:45 +02:00
Kuninori Morimoto
4fe12388a9 pinctrl: sh-pfc: r8a7796: Add Audio SSI pin support
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-16 11:53:44 +02:00
Kuninori Morimoto
07073b8858 pinctrl: sh-pfc: r8a7796: Rename SSI_{WS,SCK}34 to SSI_{WS,SCK}349
R-Car Gen3 is using SSI_{WS,SCK}349 instead of SSI_{WS,SCK}34.
But, current code is based on old datasheet which had typo.
This patch fixes this typo.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-16 11:53:37 +02:00
Kuninori Morimoto
540403265b pinctrl: sh-pfc: r8a7796: Rename SSI_{WS,SCK}0129 to SSI_{WS,SCK}01239
Based on Rev 0.50 or later R-Car Gen3 datasheet.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:50:43 +02:00
Geert Uytterhoeven
41397032c4 pinctrl: sh-pfc: r8a7796: Add group for AVB MDIO and MII pins
Group the AVB pins into similar groups as found in other sh-pfc drivers.
The pins can not be muxed between functions other than AVB, but their
drive strengths can be controlled.

The group avb_mdc containing ADV_MDC and ADV_MDIO is called avb_mdio on
R-Car Gen2 SoCs.  In pfc-r8a7796 the avb_mdc group already existed and
is in use in DT. Therefore add the ADV_MDIO pin to the existing group
instead of renaming it.

Based on commit b25719eb93 ("pinctrl: sh-pfc: r8a7795: Add group
for AVB MDIO and MII pins").

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2017-05-15 09:50:43 +02:00
Takeshi Kihara
332cb226f7 pinctrl: sh-pfc: r8a7796: Add PWM pins, groups and functions
This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to
R8A7796 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:50:43 +02:00
Sergei Shtylyov
e1b5f32dc2 pinctrl: sh-pfc: r8a7791: Grand I2C rename
The R8A7791 PFC driver was apparently based on the preliminary revisions
of the user's manual, which called all the I2C signals {SCL|SDA}<n> and
MOD_SEL register fields SEL_IIC<n> without making a difference between
two types of the I2C controllers used.  The recent manual calls the
signals {I2C|IIC}<n>_{SCL|SDA> and the MOD_SEL fields SEL_{I2C|IIC}<n>
finally making this difference.  Follow the suit...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:50:43 +02:00
Linus Torvalds
68fed41e0f This is the bulk of pin control changes for the v4.12 cycle:
Core changes:
 
 - Add bi-directional and output-enable pin configurations to
   the generic bindings and generic pin controlling core.
 
 New drivers or subdrivers:
 
 - Armada 37xx SoC pin controller and GPIO support.
 
 - Axis ARTPEC-6 SoC pin controller support.
 
 - AllWinner A64 R_PIO controller support, and opening up the
   AllWinner sunxi driver for ARM64 use.
 
 - Rockchip RK3328 support.
 
 - Renesas R-Car H3 ES2.0 support.
 
 - STM32F469 support in the STM32 driver.
 
 - Aspeed G4 and G5 pin controller support.
 
 Improvements:
 
 - A whole slew of realtime improvements to drivers implementing
   irqchips: BCM, AMD, SiRF, sunxi, rockchip.
 
 - Switch meson driver to get the GPIO ranges from the device
   tree.
 
 - Input schmitt trigger support on the Rockchip driver.
 
 - Enable the sunxi (AllWinner) driver to also be used on ARM64
   silicon.
 
 - Name the Qualcomm QDF2xxx GPIO lines.
 
 - Support GMMR GPIO regions on the Intel Cherryview. This
   fixes a serialization problem on these platforms.
 
 - Pad retention support for the Samsung Exynos 5433.
 
 - Handle suspend-to-ram in the AT91-pio4 driver.
 
 - Pin configuration support in the Aspeed driver.
 
 Cleanups:
 
 - The final name of Rockchip RK1108 was RV1108 so rename the
   driver and variables to stay consistent.
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Merge tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.12 cycle.

  The extra week before the merge window actually resulted in some of
  the type of fixes that usually arrive after the merge window already
  starting to trickle in from eager developers using -next, I'm
  impressed.

  I have recruited a Samsung subsubsystem maintainer (Krzysztof) to deal
  with the onset of Samsung patches. It works great.

  Apart from that it is a boring round, just incremental updates and
  fixes all over the place, no serious core changes or anything exciting
  like that. The most pleasing to see is Julia Cartwrights work to audit
  the irqchip-providing drivers for realtime locking compliance. It's
  one of those "I should really get around to looking into that" things
  that have been on my TODO list since forever.

  Summary:

  Core changes:

   - add bi-directional and output-enable pin configurations to the
     generic bindings and generic pin controlling core.

  New drivers or subdrivers:

   - Armada 37xx SoC pin controller and GPIO support.

   - Axis ARTPEC-6 SoC pin controller support.

   - AllWinner A64 R_PIO controller support, and opening up the
     AllWinner sunxi driver for ARM64 use.

   - Rockchip RK3328 support.

   - Renesas R-Car H3 ES2.0 support.

   - STM32F469 support in the STM32 driver.

   - Aspeed G4 and G5 pin controller support.

  Improvements:

   - a whole slew of realtime improvements to drivers implementing
     irqchips: BCM, AMD, SiRF, sunxi, rockchip.

   - switch meson driver to get the GPIO ranges from the device tree.

   - input schmitt trigger support on the Rockchip driver.

   - enable the sunxi (AllWinner) driver to also be used on ARM64
     silicon.

   - name the Qualcomm QDF2xxx GPIO lines.

   - support GMMR GPIO regions on the Intel Cherryview. This fixes a
     serialization problem on these platforms.

   - pad retention support for the Samsung Exynos 5433.

   - handle suspend-to-ram in the AT91-pio4 driver.

   - pin configuration support in the Aspeed driver.

  Cleanups:

   - the final name of Rockchip RK1108 was RV1108 so rename the driver
     and variables to stay consistent"

* tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
  pinctrl: mediatek: Add missing pinctrl bindings for mt7623
  pinctrl: artpec6: Fix return value check in artpec6_pmx_probe()
  pinctrl: artpec6: Remove .owner field for driver
  pinctrl: tegra: xusb: Silence sparse warnings
  ARM: at91/at91-pinctrl documentation: fix spelling mistake: "contoller" -> "controller"
  pinctrl: make artpec6 explicitly non-modular
  pinctrl: aspeed: g5: Add pinconf support
  pinctrl: aspeed: g4: Add pinconf support
  pinctrl: aspeed: Add core pinconf support
  pinctrl: aspeed: Document pinconf in devicetree bindings
  pinctrl: Add st,stm32f469-pinctrl compatible to stm32-pinctrl
  pinctrl: stm32: Add STM32F469 MCU support
  Documentation: dt: Remove ngpios from stm32-pinctrl binding
  pinctrl: stm32: replace device_initcall() with arch_initcall()
  pinctrl: stm32: add possibility to use gpio-ranges to declare bank range
  pinctrl: armada-37xx: Add gpio support
  pinctrl: armada-37xx: Add pin controller support for Armada 37xx
  pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers
  pinctrl: core: Make pinctrl_init_controller() static
  pinctrl: generic: Add bi-directional and output-enable
  ...
2017-05-02 17:59:33 -07:00
Tony Lindgren
6118714275 pinctrl: core: Fix pinctrl_register_and_init() with pinctrl_enable()
Recent pinctrl changes to allow dynamic allocation of pins exposed one
more issue with the pinctrl pins claimed early by the controller itself.
This caused a regression for IMX6 pinctrl hogs.

Before enabling the pin controller driver we need to wait until it has
been properly initialized, then claim the hogs, and only then enable it.

To fix the regression, split the code into pinctrl_claim_hogs() and
pinctrl_enable(). And then let's require that pinctrl_enable() is always
called by the pin controller driver when ready after calling
pinctrl_register_and_init().

Depends-on: 950b0d91dc ("pinctrl: core: Fix regression caused by delayed
work for hogs")
Fixes: df61b366af26 ("pinctrl: core: Use delayed work for hogs")
Fixes: e566fc11ea ("pinctrl: imx: use generic pinctrl helpers for
managing groups")
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Mika Penttilä <mika.penttila@nextfour.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Stefan Agner <stefan@agner.ch>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Gary Bisson <gary.bisson@boundarydevices.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 01:08:08 +02:00
Sergei Shtylyov
5f4c8cafe1 pinctrl: sh-pfc: r8a7794: Swap ATA signals
All R8A7794 manuals I have here (0.50 and 1.10) agree that the PFC driver
has ATAG0# and ATAWR0# signals in IPSR12 swapped -- fix this.

Fixes: 43c4436e2f ("pinctrl: sh-pfc: add R8A7794 PFC support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-04-05 09:41:29 +02:00
Sergei Shtylyov
0cbdc11482 pinctrl: sh-pfc: r8a7791: Fix IPSR comment typos
The IPSR field names in the comments have been fat-fingered in a couple
places --  fix those silly typos...

Fixes: 5088451962 ("pinctrl: sh-pfc: r8a7791 PFC support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-04-04 09:22:27 +02:00
Sergei Shtylyov
58439280f8 pinctrl: sh-pfc: r8a7791: Fix SCIF2 pinmux data
PINMUX_IPSR_MSEL() macro invocation for the TX2 signal has apparently wrong
1st argument -- most probably a result of cut&paste programming...

Fixes: 5088451962 ("pinctrl: sh-pfc: r8a7791 PFC support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-04-04 09:22:26 +02:00
Sergei Shtylyov
3908632fb8 pinctrl: sh-pfc: r8a7791: Add missing DVC_MUTE signal
The R8A7791 PFC driver  was apparently based on the preliminary revisions
of  the user's  manual, which  omitted the DVC_MUTE signal  altogether in
the PFC section. The modern manual has the signal described,  so just add
the necassary data to the driver...

Fixes: 5088451962 ("pinctrl: sh-pfc: r8a7791 PFC support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-04-04 09:22:26 +02:00
Sergei Shtylyov
da7a692fbb pinctrl: sh-pfc: r8a7791: Add missing HSCIF1 pinmux data
The R8A7791 PFC driver  was apparently based on the preliminary revisions
of  the  user's manual, which  omitted the HSCIF1 group E signals in  the
IPSR4 register description. This would cause HSCIF1's probe  to fail with
the messages like below:

sh-pfc e6060000.pfc: cannot locate data/mark enum_id for mark 1989
sh-sci e62c8000.serial: Error applying setting, reverse things back
sh-sci: probe of e62c8000.serial failed with error -22

Add the neceassary PINMUX_IPSR_MSEL() invocations for the HSCK1_E,
HCTS1#_E, and HRTS1#_E signals...

Fixes: 5088451962 ("pinctrl: sh-pfc: r8a7791 PFC support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-04-04 09:22:25 +02:00
Geert Uytterhoeven
d14a39edf7 pinctrl: sh-pfc: r8a7795: Add SCIF_CLK support
Add pins, groups, and a function for SCIF_CLK on R-Car H3 ES2.0.
SCIF_CLK is the external clock source for the Baud Rate Generator for
External Clock (BRG) on (H)SCIF serial ports.

Extracted from a big patch in the BSP by Takeshi Kihara.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
2017-03-30 13:43:55 +02:00
Geert Uytterhoeven
e7ad4d3c1d pinctrl: sh-pfc: r8a7795: Add SCIF support
Add pins, groups, and functions for all SCIF serial ports on R-Car H3
ES2.0.

Extracted from a big patch in the BSP by Takeshi Kihara.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
2017-03-30 13:43:51 +02:00
Geert Uytterhoeven
b205914c8f pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0
The Pin Function Controller module in the R-Car H3 ES2.0 differs from
ES1.x in many ways.

The goal is twofold:
  1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
     for now,
  2. Make it clear which code supports ES1.x, so it can easily be
     identified and removed later, when production SoCs are deemed
     ubiquitous.

Hence this patch:
  1. Extracts the support for R-Car H3 ES1.x into a separate file, as
     the differences are quite large,
  2. Adds code for detecting the SoC revision at runtime using the new
     soc_device_match() API, and selecting pinctrl tables for the actual
     SoC revision,
  3. Replaces the core register and bitfield definitions by their
     counterparts for R-Car H3 ES2.0.

The addition of pins, groups, and functions for the various on-chip
devices is left to subsequent patches.

The R-Car H3 ES2.0 register and bitfield definitions were extracted from
a patch in the BSP by Takeshi Kihara.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
2017-03-30 13:43:45 +02:00
Geert Uytterhoeven
3091ae775f pinctrl: sh-pfc: Update info pointer after SoC-specific init
Update the sh_pfc_soc_info pointer after calling the SoC-specific
initialization function, as it may have been updated to e.g. handle
different SoC revisions.  This makes sure the correct subdriver name is
printed later.

Fixes: 0c151062f3 ("sh-pfc: Add support for SoC-specific initialization")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21 11:21:55 +01:00
Geert Uytterhoeven
b332da51a9 pinctrl: sh-pfc: r8a7795: Restore sort order
Somehow the QSPI and SCIF_CLK fragments were inserted at the wrong
positions.  Restore sort order (alphabetically, per group).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21 11:17:38 +01:00
Geert Uytterhoeven
4324b6084f pinctrl: sh-pfc: r8a7795: Fix hscif2_clk_b and hscif4_ctrl
Fix typos in hscif2_clk_b_mux[] and hscif4_ctrl_mux[].

Fixes: a56069c46c ("pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and functions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-21 11:17:15 +01:00
Linus Walleij
7469426911 pinctrl: sh-pfc: Updates for v4.11 (take two)
- Add Gyro-ADC pin groups for R-Car M2-W.
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Merge tag 'sh-pfc-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.11 (take two)

  - Add Gyro-ADC pin groups for R-Car M2-W.
2017-01-30 14:58:57 +01:00
Jacopo Mondi
07254d835d pinctrl: sh-pfc: r8a7791: Add ADI pinconf support
Add pin configuration support for Gyro-ADC, named ADI on r8a7791 SoC.

Signed-off-by: Jacopo Mondi <jacopo@jmondi.org>
Tested-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-01-20 14:23:40 +01:00
Linus Walleij
537e18b228 pinctrl: sh-pfc: Updates for v4.11
- Add bias handling for non-GPIO pins for R-Car H3,
   - Add drive-strength and bias handling for R-Car M3-W,
   - Add CAN, CAN FD, MSIOF, and HSCIF pin groups for R-Car M3-W,
   - Add SDHI voltage switching for R-Car M2-N.
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Merge tag 'sh-pfc-for-v4.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.11

  - Add bias handling for non-GPIO pins for R-Car H3,
  - Add drive-strength and bias handling for R-Car M3-W,
  - Add CAN, CAN FD, MSIOF, and HSCIF pin groups for R-Car M3-W,
  - Add SDHI voltage switching for R-Car M2-N.
2017-01-13 16:43:17 +01:00
Tony Lindgren
950b0d91dc pinctrl: core: Fix regression caused by delayed work for hogs
Commit df61b366af26 ("pinctrl: core: Use delayed work for hogs") caused a
regression at least with sh-pfc that is also a GPIO controller as
noted by Geert Uytterhoeven <geert@linux-m68k.org>.

As the original pinctrl_register() has issues calling pin controller
driver functions early before the controller has finished registering,
we can't just revert commit df61b366af26. That would break the drivers
using GENERIC_PINCTRL_GROUPS or GENERIC_PINMUX_FUNCTIONS.

So let's fix the issue with the following steps as a single patch:

1. Revert the late_init parts of commit df61b366af26.

   The late_init clearly won't work and we have to just give up
   on fixing pinctrl_register() for GENERIC_PINCTRL_GROUPS and
   GENERIC_PINMUX_FUNCTIONS.

2. Split pinctrl_register() into two parts

   By splitting pinctrl_register() into pinctrl_init_controller()
   and pinctrl_create_and_start() we have better control over when
   it's safe to call pinctrl_create().

3. Introduce a new pinctrl_register_and_init() function

   As suggested by Linus Walleij <linus.walleij@linaro.org>, we
   can just introduce a new function for the controllers that need
   pinctrl_create() called later.

4. Convert the four known problem cases to use new function

   Let's convert pinctrl-imx, pinctrl-single, sh-pfc and ti-iodelay
   to use the new function to fix the issues. The rest of the drivers
   can be converted later. Let's also update Documentation/pinctrl.txt
   accordingly because of the known issues with pinctrl_register().

Fixes: df61b366af26 ("pinctrl: core: Use delayed work for hogs")
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-13 16:25:17 +01:00
Ulrich Hecht
0e4e4999aa pinctrl: sh-pfc: r8a7796: Add HSCIF pins, groups, and functions
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
[geert: Fix hscif2_clk_[bc]_mux[] and hscif4_ctrl_mux[]]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27 10:57:39 +01:00
Simon Horman
aa6931f135 pinctrl: sh-pfc: r8a7793: Implement voltage switching for SDHI
Voltage switching is the same as on the r8a7791.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27 10:57:39 +01:00
Takeshi Kihara
4753231cc9 pinctrl: sh-pfc: r8a7796: Add MSIOF pins, groups and functions
This patch adds MSIOF{0,1,2,3} pins, groups and functions to R8A7796
SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Correct MSIOF3 SS1_E/SS2_E pins]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27 10:57:39 +01:00
Chris Paterson
3dc93dcea6 pinctrl: sh-pfc: r8a7796: Add CAN FD support
This patch adds CAN FD[0-1] pinmux support to r8a7796 SoC.

Based on a patch for r8a7795 by Ramesh Shanmugasundaram.

Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27 10:57:38 +01:00
Chris Paterson
cf75341acc pinctrl: sh-pfc: r8a7796: Add CAN support
This patch adds CAN[0-1] pinmux support to r8a7796 SoC.

Based on a patch for r8a7795 by Ramesh Shanmugasundaram.

Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27 10:57:38 +01:00
Niklas Söderlund
4c2fb44d60 pinctrl: sh-pfc: r8a7795: Support none GPIO pins bias setting
There are pins on the r8a7795 which are not part of a GPIO bank nor
can be muxed between different functions. They do however allow for the
bias to be configured. Add those pins to the list of pins and
to the bias configuration array.

The pins can now be referred to in DT by function names and their bias
setting set.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27 10:57:38 +01:00
Niklas Söderlund
2d40bd2427 pinctrl: sh-pfc: r8a7796: Add bias pinconf support
Implements pull-up and pull-down. On this SoC there is no simple mapping
of GP pins to bias register bits, so we need a table.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27 10:57:38 +01:00
Niklas Söderlund
9e35d6fa82 pinctrl: sh-pfc: r8a7796: Add drive strength support
Define the drive strength registers for the R8A7796. Add pins which are
not part of a GPIO bank nor can be muxed between different functions but
which still allow for their drive-strength to be configured.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27 10:57:38 +01:00
Niklas Söderlund
1fa1522f61 pinctrl: sh-pfc: r8a7795: Add group for QSPI0 and QSPI1 pins
Group the QSPI0 and QSPI1 pins into similar groups found in other sh-pfc
drivers. The pins can not be muxed between functions other than QSPI,
but their drive strength can be controlled.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-16 10:29:14 +01:00
Niklas Söderlund
b25719eb93 pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pins
Group the AVB pins into similar groups found in other sh-pfc drivers.
The pins can not be muxed between functions other then AVB but their
drive strength can be controlled.

The group avb_mdc containing ADV_MDC and ADV_MDIO are on other SoCs
called avb_mdio. In pfc-r8a7795 the avb_mdc group already existed and
is in use in DT. Therefore add the ADV_MDIO pin to the existing group
instead of renaming it.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-16 10:29:13 +01:00
Niklas Söderlund
ea9c740583 pinctrl: sh-pfc: r8a7795: Support none GPIO pins with configurable drive-strength
There are pins on the r8a7795 which are not part of a GPIO bank nor
can be muxed between different functions. They do however allow for the
drive-strength to be configured. Add those pins to the list of pins and
to the drive-strength configuration registers.

The pins can now be referred to in DT by function names and their
drive-strength modified.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-16 10:29:12 +01:00
Niklas Söderlund
1ce56aea7c pinctrl: sh-pfc: Support named pins with custom configuration
Pins not associated with a GPIO port can still have other configuration
parameters. Add a new macro SH_PFC_PIN_NAMED_CFG which allows for named
pins to be declared with a set of configurations. The new macro is an
modification of SH_PFC_PIN_NAMED to allow for optional configuration to
be assigned.

The flag SH_PFC_PIN_CFG_NO_GPIO is still enforced as this should only be
used to define pins not associated with a GPIO port.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-16 10:29:12 +01:00
Niklas Söderlund
5c296f69ab pinctrl: sh-pfc: r8a7778: Use lookup function for bias data
Change the data structure and use the generic sh_pfc_pin_to_bias_info()
function to get the register offset and bit information.

Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-16 10:29:11 +01:00
Niklas Söderlund
d3b861bccd pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
There is a bug in the r8a7795 bias code where a WARN() is trigged
anytime a pin from PUEN0/PUD0 is accessed.

 # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins

 WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8
 [..]
 Call trace:
 [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
 [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
 [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
 [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
 [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
 [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
 [<ffff0000081fe3bc>] seq_read+0x16c/0x420
 [<ffff00000831a110>] full_proxy_read+0x58/0x88
 [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
 [<ffff0000081d8874>] vfs_read+0x84/0x148
 [<ffff0000081d9d64>] SyS_read+0x44/0xa0
 [<ffff000008082f4c>] __sys_trace_return+0x0/0x4

This is due to the WARN() check if the reg field of the pullups struct
is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
registers since PU0 is defined as 0. Change the data structure and use
the generic sh_pfc_pin_to_bias_info() function to get the register
offset and bit information.

Fixes: 560655247b ("pinctrl: sh-pfc: r8a7795: Add bias pinconf support")
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-16 10:29:10 +01:00
Niklas Söderlund
42831cf965 pinctrl: sh-pfc: r8a7795: Simplify get bias logic
The last else statement is missing braces, and the indentation level can
be reduced.

Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-16 10:28:58 +01:00
Niklas Söderlund
c314c9f15a pinctrl: sh-pfc: Add helper to handle bias lookup table
On some SoC there are no simple mapping of pins to bias register bits
and a lookup table is needed. This logic is already implemented in some
SoC specific drivers that could benefit from a generic implementation.

Add helpers to deal with the lookup which later can be used by the SoC
specific drivers. The logic used to lookup are different from the one it
aims to replace, this is intentional. This new method reduces the memory
consumption at the cost of increased CPU usage and fix a bug where a
WARN() would incorrectly be triggered if the register offset is 0.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-15 11:01:09 +01:00
Niklas Söderlund
5d7400c4ac pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE
Always stating PIN_CONFIG_BIAS_DISABLE is supported gives untrue output
when examining /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins if
the operation get_bias() is implemented but the pin is not handled by
the get_bias() implementation. In that case the output will state that
"input bias disabled" indicating that this pin has bias control
support.

Make support for PIN_CONFIG_BIAS_DISABLE depend on that the pin either
supports SH_PFC_PIN_CFG_PULL_UP or SH_PFC_PIN_CFG_PULL_DOWN. This also
solves the issue where SoC specific implementations print error messages
if their particular implementation of {set,get}_bias() is called with a
pin it does not know about.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-15 11:01:09 +01:00
Niklas Söderlund
cccc618a0b pinctrl: sh-pfc: r8a7796: Add DU support
Only the DU parallel RGB output signals are included, HDMI and TCON pins
will be added in separate groups. Based on a similar patch from Laurent
Pinchart for the r8a7795 PFC driver.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-15 11:01:08 +01:00
Takeshi Kihara
9c99a63ec7 pinctrl: sh-pfc: r8a7796: Add EtherAVB pins, groups and functions
This patch adds AVB_LINK, AVB_MAGIC, AVB_PHY_INT, AVB_MDC, AVB_AVTP_PPS,
AVB_AVTP_MATCH, AVB_AVTP_CAPTURE pins, groups and functions to R8A7796
SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-15 11:01:07 +01:00