Merge "omap device tree changes for v3.15, part 2" from Tony Lindgren:
Part two of omap device tree changes enabling driver features
in the dts files.
* tag 'omap-for-v3.15/dt-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am335x-evmsk: enable dual_emac mode
ARM: dts: DRA7: Add device nodes for ABB
ARM: dts: OMAP4: Add device nodes for ABB
ARM: dts: OMAP36xx: Add device node for ABB
ARM: dts: am43x-epos-evm: add SD card hotplug support
ARM: dts: am335x-evm: add SD card hotplug support
ARM: dts: am437x gp-evm: add sd card dt nodes
ARM: dts: omap5: added dt properties to adapt to the new phy framwork
ARM: OMAP2+: Use pdata quirks for wl12xx on the AM335x EV-MSK
ARM: dts: Update echi-omap DT binding example usage
ARM: dts: Get rid of incompatible ids for hci-omap USB host nodes
ARM: OMAP2+: Remove legacy_init_ehci_clk()
ARM: dts: Add support for OMAP4 Gumstix DuoVero/Parlor
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "ARM: bcm2835: DT changes for 3.15" from Stephen Warren:
A variety of features are added to the bcm2835 device trees:
- ARM PMU, for perf_event
- DMA controller
- I2S controller
A few cleanups are applied to the DTs too.
* tag 'bcm2835-for-3.15-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
ARM: bcm2835: fix clock DT node names
ARM: bcm2835: node name unit address cleanup
ARM: bcm2835: fix DT node sort order
ARM: bcm2835: add I2S driver to device tree
ARM: bcm2835: add dmaengine driver to device tree
ARM: bcm2835: perf_event support for Raspberry-Pi
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "ARM: mach-bcm dt updates for 3.15" from Matt Porter:
- add BCM4708 dt support
- remove bcm11351-brt
- bcm281xx common clock support
* tag 'armsoc/for-3.15/dt' of git://github.com/broadcom/mach-bcm:
ARM: dts: remove bcm11351-brt.dts
ARM: dts: Leave sdio1 as disabled on bcm28155-ap
ARM: dts: bcm281xx: define real clocks
ARM: BCM5301X: add dts files for BCM4708 SoC
Signed-off-by: Olof Johansson <olof@lixom.net>
On the newly introduced sama5d36, Gigabit and 10/100 Ethernet network
interfaces are probed in a different order than for the sama5d35.
Moreover, users are accustomed to this order in bootloaders and backports
for older kernel revisions.
So this patch switches DT node order as it is done for the other dual-Ethernet
sama5d3 SoC.
Better interface numbering which does not depend on DT node order is being
developed for stronger interface identification.
Signed-off-by: Boris BREZILLON <b.brezillon.dev@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds IRB support to STiH416 platforms.
Tested on B2000 and B2020 development board
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds IRB support to STiH415 platforms.
Tested on B2000 and B2020 development boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds support to STiH416 SOC, which has two ethernet
snps,dwmac controllers version 3.710. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds support to STiH415 SOC, which has two ethernet
snps,dwmac controllers version 3.610. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds soft reset controller support for STiH415 and adds new
softreset lines required for other device tree nodes in the header file.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds a reset controller node to the SOC device tree and also
adds new header files with reset lines required for other device tree
nodes.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds soft reset controller support for STiH415 and adds new
softreset lines required for other device tree nodes in the header file.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds a reset controller node to the SOC device tree and also
adds new header files with reset lines required for other device tree
nodes.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Add the "atmel,nand-has-dma" property to NAND node for SoC that
can use the DMA to perform NAND accesses.
Use of this property was added in 1b7192658a
(mtd: atmel_nand: add a new dt binding item for nand dma support).
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Boris BREZILLON <b.brezillon@overkiz.com>
commit[7e0b4cd dts: socfpga: Add DTS entry for adding the stmmac glue
layer for stmmac.] references the sysmgr through its phandle. This patch
adds the appropriate sysmgr node for the gmac to use.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Introduce "altr,socfpga-dw-mshc" to enable Altera's SOCFPGA platform
specific implementation of the dw_mmc driver.
Also add the "syscon" binding to the "altr,sys-mgr" node. The clock
driver can use the syscon driver to toggle the register for the SD/MMC
clock phase shift settings.
Finally, fix an indentation error for the sysmgr node.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Tested-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Chris Ball <chris@printf.net>
Pull ARM SoC fixes from from Olof Johansson:
"A collection of fixes for ARM platforms. A little large due to us
missing to do one last week, but there's nothing in particular here
that is in itself large and scary.
Mostly a handful of smaller fixes all over the place. The majority is
made up of fixes for OMAP, but there are a few for others as well. In
particular, there was a decision to rename a binding for the Broadcom
pinctrl block that we need to go in before the final release since we
then treat it as ABI"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: dts: omap3-gta04: Add ti,omap36xx to compatible property to avoid problems with booting
ARM: tegra: add LED options back into tegra_defconfig
ARM: dts: omap3-igep: fix boot fail due wrong compatible match
ARM: OMAP3: Fix pinctrl interrupts for core2
pinctrl: Rename Broadcom Capri pinctrl binding
pinctrl: refer to updated dt binding string.
Update dtsi with new pinctrl compatible string
ARM: OMAP: Kill warning in CPUIDLE code with !CONFIG_SMP
ARM: OMAP2+: Add support for thumb mode on DT booted N900
ARM: OMAP2+: clock: fix clkoutx2 with CLK_SET_RATE_PARENT
ARM: OMAP4: hwmod: Fix SOFTRESET logic for OMAP4
ARM: DRA7: hwmod data: correct the sysc data for spinlock
ARM: OMAP5: PRM: Fix reboot handling
ARM: sunxi: dt: Change the touchscreen compatibles
ARM: sun7i: dt: Fix interrupt trigger types
i.MX SoC changes for 3.15 from Shawn Guo:
- Support suspend from ocram (DDR IO floating) for imx6 platforms
- Add cpuidle support for imx6sl
- Sparse warning fixes for imx6sl and vf610 clock code
- Remove PWM platform code
- Support ptp and rmii clock from pad
- Support WEIM CS GPR configuration
- Random cleanups and defconfig updates
* tag 'imx-soc-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6: (373 commits)
ARM: imx6: drop .text.head section annotation from headsmp.S
ARM: imx6: build suspend-imx6.o with CONFIG_SOC_IMX6
ARM: imx6: rename pm-imx6q.c to pm-imx6.c
ARM: imx6: introduce CONFIG_SOC_IMX6 for i.MX6 common stuff
ARM: imx6: do not call imx6q_suspend_init() with !CONFIG_SUSPEND
ARM: imx6: call suspend_set_ops() from suspend routine
ARM: imx6: build headsmp.o only on CONFIG_SMP
ARM: imx6: move v7_cpu_resume() into suspend-imx6.S
ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority
ARM: imx6q: Add GPR6 and GPR7 register definitions for iomuxc gpr
bus: imx-weim: support CS GPR configuration
ARM: mach-imx: Kconfig: Remove IMX_HAVE_PLATFORM_IMX2_WDT from SOC_IMX53
ARM: imx_v6_v7_defconfig: Select CONFIG_DEBUG_FS
ARM: mach-imx: Select CONFIG_SRAM at ARCH_MXC level
ARM: imx: add speed grading check for i.mx6 soc
ARM: imx: avoid calling clk APIs in idle thread which may cause schedule
ARM: imx6q: support ptp and rmii clock from pad
ARM: imx6q: remove unneeded clk lookups
ARM: imx_v6_v7_defconfig: Select CONFIG_MMC_UNSAFE_RESUME
ARM: imx_v4_v5_defconfig: Select CONFIG_MMC_UNSAFE_RESUME
...
i.MX6 device tree changes for 3.15, take 2 from Shawn Guo:
- Add USB, GPMI and SATA support for imx6q-phytec board
- Update imx6sl-evk board support regarding PFUZE100, audio and
LED etc.
- Minor updates on a few imx6qdl boards
* tag 'imx6-dt-3.15-2' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: dts: imx6q-phytec: Added SATA Support
ARM: dts: imx6q-phytec: Added GPMI-NAND Support
ARM: dts: imx6q-phytec: Added USB_HOST Support
ARM: dts: imx6q-phytec: Added USB_OTG Support
ARM: dts: imx6sl-evk: Keep VGEN1 regulator always enabled
ARM: dts: imx6qdl-sabreauto: Support debug LED
ARM: dts: imx6q: add 852MHz setpoint for CPU freq
ARM: dts: imx6qdl-wandboard: use GPIO_6 for FEC interrupt
ARM: dts: imx6sl-evk: Add debug LED support
ARM: dts: imx6qdl-sabreauto: Add PFUZE100 support
ARM: dts: imx6sl-evk: Add audio support
ARM: dts: imx6sl-evk: Add PFUZE100 support
ARM: dts: imx6qdl-sabresd: correct gpio key's active state
Signed-off-by: Olof Johansson <olof@lixom.net>
ARM: sirf: machine update for 3.15 from Barry Song:
Most of the below are some minor fixes for coding style. "ARM: prima2:
move to generic reset controller driver framework" has been ready near
3.14 merge window, but it was late to merge in 3.14, so move this one
to 3.15.
* tag 'sirf-soc-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux:
ARM: prima2: move to generic reset controller driver framework
ARM: prima2: staticize sirfsoc_init_late function
ARM: prima2: rtciobrg: fix the typo about license
ARM: prima2: common: fix checkpatch issues
ARM: prima2: platsmp: fix checkpatch issues
ARM: prima2: l2x0: fix checkpatch issues
Signed-off-by: Olof Johansson <olof@lixom.net>
A set of device tree-related cleanups for the ux500 platform from Linus
Walleij:
- Rename SSP/SPI clocks to the name found in the hardware
reference manual. (Also includes a rename in the U300
device tree file.)
- Delete dead non-DT code.
- Drop now completely unused GPIO definition header file.
- Delete all hardcoded IRQ number assignments. This hits
MFD a bit so the patch has been ACKed by Lee Jones from
the MFD side.
* tag 'ux500-dt-v3.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
mfd: dbx500/abx500: root out hardcoded IRQ assignments
ARM: ux500: drop a chunk of GPIO definitions
ARM: ux500: skip GIC CPU and dist address checks
ARM: ux500: delete pointless DT config option
ARM: u300: switch SSP/SPI clock name to "SSPCLK"
ARM: ux500: switch SSP/SPI clock name to "SSPCLK"
Signed-off-by: Olof Johansson <olof@lixom.net>
Samsung exynos clock related DT updates for v3.15 from Kukjim Kim:
- use macros instead of hard coded numbers for clock bindings
NOTE: this is based on v3.15-next/dt-samsung
* tag 'exynos-clk' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: use macros in clock bindings for exynos5440
ARM: dts: use macros in clock bindings for exynos5420
ARM: dts: use macros in clock bindings for exynos5250
ARM: dts: use macros in clock bindings for exynos4
Samsung DT updates for v3.15 from Kukjin Kim:
For exynos4412
- update vdd_arm voltage range for odroidx board
For exynos5250
- add PMU sysreg node and update watchdog node
- re-organize RTC status
- add max77686 pmic node for smdk5250
For exynos5420
- add PMU sysreg, i2s, adma and watchdog nodes
- re-organize RTC status
- add fixed voltage regulators and regulator nodes
for smdk5420
- add PMIC, GPIO based wake up key and vmmc-supply
support for arndale-octa board
* tag 'samsung-dt' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: Add vmmc-supply to MMC on arndale-octa board
ARM: dts: Add wake up key to arndale-octa board
ARM: dts: Add PMIC support to arndale-octa board
ARM: dts: Add fixed voltage regulators to smdk5420
ARM: dts: Add I2S nodes to exynos5420
ARM: dts: Add ADMA node to exynos5420
ARM: dts: Re-organize RTC status for exynos5250
ARM: dts: Re-organize RTC status for exynos5420
ARM: dts: Add regulator entries to smdk5420
ARM: dts: add max77686 pmic node for smdk5250
ARM: dts: update vdd_arm voltage range for exynos4412 based boards
ARM: dts: update watchdog device nodes for exynos5250 and exynos5420
ARM: dts: Add pmu sysreg node to exynos5250 and exynos5420
Signed-off-by: Olof Johansson <olof@lixom.net>
From Tony Lindgren:
Two omap3430 vs 3630 device tree regression fixes for
issues booting 3430 based boards.
* tag 'omap-for-v3.14/fixes-dt-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap3-gta04: Add ti,omap36xx to compatible property to avoid problems with booting
ARM: dts: omap3-igep: fix boot fail due wrong compatible match
Signed-off-by: Olof Johansson <olof@lixom.net>
* integrator/multiplatform-base:
ARM: integrator: select GPIO block
ARM: integrator: register the IM-PD1 VIC
ARM: integrator: use managed resources for the IM-PD1
irqchip: support cascaded VICs
irqchip: vic: update the base IRQ member correctly
clk: versatile: respect parent rate in ICST clock
clk: versatile: pass a parent to the ICST clock
ARM: integrator: switch to fetch clocks from device tree
ARM: SP804: make Integrator/CP timer pick clock from DT
ARM: integrator: define clocks in the device trees
Merge 'bcm pinctrl rename' From Christin Daudt:
Rename pinctrl dt binding to restore consistency with other bcm mobile
bindings.
* tag 'bcm-for-3.14-pinctrl-reduced-rename' of git://github.com/broadcom/bcm11351:
pinctrl: Rename Broadcom Capri pinctrl binding
pinctrl: refer to updated dt binding string.
Update dtsi with new pinctrl compatible string
+ Linux 3.14-rc4
Signed-off-by: Olof Johansson <olof@lixom.net>
Allwinner fixes from Maxime Ripard:
Two fixes for device trees additions that got added in 3.14. One fixes the
interrupt types of some IPs, the other fixes up a compatible that got
introduced during 3.14
* tag 'sunxi-fixes-for-3.14' of https://github.com/mripard/linux:
ARM: sunxi: dt: Change the touchscreen compatibles
ARM: sun7i: dt: Fix interrupt trigger types
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch connects IPU and display encoder (HDMI, LVDS, MIPI)
device tree nodes, as well as parallel displays on the DISP0
and DISP1 outputs, using the OF graph bindings described in
Documentation/devicetree/bindings/media/video-interfaces.txt
The IPU ports correspond to the two display interfaces. The
order of endpoints in the ports is arbitrary.
Each encoder with an associated input multiplexer has multiple
input ports in the device tree. The order and reg property of
the ports must correspond to the multiplexer input order.
Since the imx-drm node now only needs to contain links to the
display interfaces, it can be moved to the SoC dtsi level. At
the board level, only connections between the display interface
ports and encoders or panels have to be added.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch connects IPU and display encoder (VGA, LVDS)
device tree nodes, as well as parallel displays on the DISP0
and DISP1 outputs, using the OF graph bindings described in
Documentation/devicetree/bindings/media/video-interfaces.txt
The IPU ports correspond to the two display interfaces. The
order of endpoints in the ports is arbitrary.
Since the imx-drm node now only needs to contain links to the
display interfaces, it can be moved to the SoC dtsi level. At
the board level, only connections between the display interface
ports and encoders or panels have to be added.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch connects IPU and and parallel display device tree
nodes using the OF graph bindings described in
Documentation/devicetree/bindings/media/video-interfaces.txt
The IPU ports correspond to the two display interfaces. The
order of endpoints in the ports is arbitrary.
Since the imx-drm node now only needs to contain links to the
display interfaces, it can be moved to the SoC dtsi level. At
the board level, only connections between the display interface
ports and panels have to be added.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch fixes the Television Encoder node's DDC I2C bus property to
use the common property name of 'ddc-i2c-bus' instead of just 'ddc'.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The A31 Colombus board has 3 I2C controllers that should be usable. However,
the first one is not working for some reason on the hardware I have been able
to test it on, while it should really be the same controller. Enable the i2c1
and i2c2 busses, and mark i2c0 as in failure in the DT.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The i2c controllers have a few muxing options on the A31. Enable the
ones found in the A31 Colombus board.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A31 has 4 I2C controllers that are the same than the one in the
other Allwinner SoCs, except for the fact that they are asserted in
reset by the reset unit.
Add these i2c controllers to the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Marvell Dove's pinctrl does require some PMU regs for muxing PMU
functions to MPP pins. Recently, a discussion started about consolidating
Power Management Unit (PMU) into a single DT node. As we don't want
anymore DT ABI in the way, drop the corresponding reg property from
pinctrl node now. The driver will derive the registers from existing
reg properties.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 385 RD board is the reference design board from Marvell
for the Armada 385 SoC. This commit adds a Device Tree description for
this board, which enables the following features:
* Network interfaces
* I2C bus
* Serial port
* SPI bus, with a SPI flash
* PCIe interface
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
On Armada 385 DB, while the "rgmii" PHY connection mode works fine
with the generic PHY driver, it fails to work when the Marvell PHY
driver is enabled in the kernel configuration, due to a finer handling
of the PHY configuration. This is due to the fact that the phy
connection mode should instead be "rgmii-id", i.e with the TX/RX delay
mechanisms enabled.
This fixes the network operation on Armada 385 DB with
CONFIG_MARVELL_PHY=y. Without this patch and this option enabled, one
would only get messages such as:
mvneta f1070000.ethernet eth1: bad rx status 0cc10000 (crc error), size=70
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Since the Armada XP Matrix board has 4 GB of RAM and not 2 GB, we
update the Device Tree to take into account the correct amount of
memory. As noted in the new comment, the last 256 MB of RAM are in
fact not usable, due to the overlap with the MBus Window address
range.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Marvell has now provided bootloaders that are Device Tree capable for
the Armada XP GP board, and that also remap the internal register base
address to 0xf1000000. In addition, the bootloader now sets the MBus
Window base address to 0xf0000000, which allows to use much more RAM
in the last GB of RAM before the 4 GB limit (the entire space from
0xC0000000 to 0xFFFFFFFF was not usable due to being used for I/O, not
only the space from 0xF0000000 to 0xFFFFFFFF is used for I/O).
Therefore this commit:
* Updates the memory->reg Device Tree property with the fact that in
the first bank of RAM, memory up to 0xf0000000 can be used.
* Updates the soc->ranges Device Tree property with the fact that the
internal registers are now mapped at 0xf1000000.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Marvell has now provided bootloaders that are Device Tree capable for
the Armada XP DB board, and that also remap the internal register base
address to 0xf1000000. In addition, the bootloader now sets the MBus
Window base address to 0xf0000000, but on this board, this change
doesn't make much difference since the board is by default equipped
with 2 GB of RAM.
Therefore this commit updates the soc->ranges Device Tree property
with the fact that the internal registers are now mapped at
0xf1000000.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The latest Marvell bootloaders for various boards change the MBus
Window base address from 0xC0000000 to 0xF0000000, in order to make
more RAM in the first 4 GB actually usable by the kernel (RAM that is
covered by the MBus window is "shadowed" and therefore not usable).
However, our default PCIe memory and I/O apertures where sitting at
0xe0000000 (for memory) and 0xe8000000 (for I/O), which will now be
outside of the MBus Window range on those platforms. To make things
work, we have to ensure those apertures use addresses in the
0xF0000000 -> 0xFFFFFFFF range.
Of course this change of the MBus Window base address from 0xC0000000
to 0xF0000000 also comes with a change of the internal register base
address from 0xD0000000 to 0xF1000000.
We have therefore designed the following memory map:
* 0xF0000000 -> 0xF1000000: 16 MB, used for NOR flashes on Armada XP
GP and Armada XP DB.
* 0xF1000000 -> 0xF1100000: 1 MB, used for internal registers.
* 0xF8000000 -> 0xFFE00000: 126 MB, used for PCIe memory.
* 0xFFE00000 -> 0xFFF00000: 1 MB, used for PCIe I/O.
* 0xFFF00000 -> 0xFFFFFFFF: 1 MB, used for the BootROM mapping
There is one exception to this layout: the Armada XP OpenBlocks, which
has a 128 MB NOR flash, mapped from 0xF0000000 to 0xF8000000. This
does not conflict with the current change for the PCIe I/O and memory
apertures, and continues to work because on Armada XP OpenBlocks, the
bootloader is an old one, and continues to have internal registers
mapped at 0xD0000000.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Tegra124 can support 4GB of RAM. With that much RAM (plus some memory-
mapped IO peripherals), more than 32-bits of physical address space is
required. Hence, convert all Tegra124 DTs to use 2 DT cells for address
space.
(I think this was suggested by Olof Johansson, but I'm not 100% sure)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
EVM board provides two Ethernet ports, this patch sets them into
dual_emac mode to provide two independent network interfaces.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
