drivers/clk/socfpga/clk-agilex.c:24:37: warning: ‘cntr_mux’ defined but not used [-Wunused-const-variable=]
static const struct clk_parent_data cntr_mux[] = {
^~~~~~~~
There is no caller in tree, so can remove it.
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lore.kernel.org/r/20200915020950.4688-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
'err' is assigned but never read:
/drivers/clk/clk-si5341.c: In function ‘si5341_output_get_parent’:
drivers/clk/clk-si5341.c:886:6: warning: variable ‘err’ set but not used [-Wunused-but-set-variable]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200916161740.14173-5-krzk@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
'clk' is assigned but never read:
drivers/clk/mmp/clk-of-pxa1928.c: In function ‘pxa1928_pll_init’:
drivers/clk/mmp/clk-of-pxa1928.c:71:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200916161740.14173-4-krzk@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The at91sam9g45_pcr_layout is not used so drop it to fix build warning:
drivers/clk/at91/at91sam9g45.c:49:36: warning:
'at91sam9g45_pcr_layout' defined but not used [-Wunused-const-variable=]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20200916161740.14173-1-krzk@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add missing kerneldoc to fix compile warning:
drivers/clk/davinci/da8xx-cfgchip.c:578: warning: Function parameter or member 'dev' not described in 'da8xx_cfgchip_register_usb1_clk48'
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: David Lechner <david@lechnology.com>
Link: https://lore.kernel.org/r/20200916161740.14173-3-krzk@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add missing kerneldoc to fix compile warnings like:
drivers/clk/clk-fixed-factor.c:211: warning: Function parameter or member 'node' not described in 'of_fixed_factor_clk_setup'
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200916161740.14173-2-krzk@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The driver was using subsys_initcall() because in old times deferred
probe was not supported everywhere and specific ordering was needed.
Since probe deferral works fine and specific ordering is discouraged
(hides dependencies between drivers and couples their boot order), the
driver can be converted to regular module_platform_driver.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200921203558.19554-1-krzk@kernel.org
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
To use QHD or higher, we need to modify the pixel_bvb_clk value. So
add register to control this clock.
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Link: https://lore.kernel.org/r/20200901040759.29992-2-hoegeun.kwon@samsung.com
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Minor refactoring removing most of the __clk_lookup() calls.
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Merge tag 'clk-v5.10-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung
Pull Samsung clk driver updates from Sylwester Nawrocki:
Minor refactoring removing most of the __clk_lookup() calls.
* tag 'clk-v5.10-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: Use cached clk_hws instead of __clk_lookup() calls
clk: samsung: exynos5420/5250: Add IDs to the CPU parent clk definitions
clk: samsung: Add clk ID definitions for the CPU parent clocks
clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks
clk: samsung: exynos5420: Add definition of clock ID for mout_sw_aclk_g3d
clk: samsung: Keep top BPLL mux on Exynos542x enabled
- A series from Anson Huang to support building i.MX ARMv8 platforms
clock driver as module.
- Remove i.MX21 clock driver, as i.MX21 platform support is being
dropped.
- A couple of minor imx8mp clock correction from Jacky Bai.
- Add clock for CRC block found on vf610 SoC.
- A couple of clock flag fix-up from Peng Fan.
- Minor kerneldoc fix-up for i.MX clock drivers.
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Merge tag 'clk-imx-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx
Pull i.MX clk driver updates from Shawn Guo:
- A series from Anson Huang to support building i.MX ARMv8 platforms clock driver as module
- Remove i.MX21 clock driver, as i.MX21 platform support is being dropped
- A couple of minor imx8mp clock correction from Jacky Bai
- Add clock for CRC block found on vf610 SoC
- A couple of clock flag fix-up from Peng Fan
- Minor kerneldoc fix-up for i.MX clock drivers
* tag 'clk-imx-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
clk: imx: imx21: Remove clock driver
clk: imx: gate2: Fix a few typos
clk: imx: Fix and update kerneldoc
clk: imx: fix i.MX7D peripheral clk mux flags
clk: imx: fix composite peripheral flags
clk: imx: Correct the memrepair clock on imx8mp
clk: imx: Correct the root clk of media ldb on imx8mp
clk: imx: vf610: Add CRC clock
clk: imx: Explicitly include bits.h
clk: imx8qxp: Support building i.MX8QXP clock driver as module
clk: imx8m: Support module build
clk: imx: Add clock configuration for ARMv7 platforms
clk: imx: Support building i.MX common clock driver as module
clk: composite: Export clk_hw_register_composite()
clk: imx6sl: Use BIT(x) to avoid shifting signed 32-bit value by 31 bits
This was likely overlooked while porting the driver upstream.
Reported-by: Pavel Dubrova <pashadubrova@gmail.com>
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200922120909.97203-1-konradybcio@gmail.com
Fixes: f2a76a2955 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The clk_rcg2_dp_determine_rate() function is used for the DP pixel clk.
This function should return the rate that can be achieved by the pixel
clk in 'struct clk_rate_request::rate' and match the logic similar to
what is seen in clk_rcg2_dp_set_rate(). But that isn't the case. Instead
the code merely bubbles the rate request up to the parent of the pixel
clk and doesn't try to do a rational approximation of the rate that
would be achieved by picking some m/n value for the RCG.
Let's change this logic so that we can assume the parent clk frequency
is fixed (it is because it's the VCO of the DP PLL that is configured
based on the link rate) and so that we can calculate what the m/n value
will be and adjust the req->rate appropriately.
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Rob Clark <robdclark@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20200916231202.3637932-10-swboyd@chromium.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This addresses the following gcc warning with "make W=1":
drivers/clk/qcom/gcc-msm8939.c:610:32: warning:
‘gcc_xo_gpll6_gpll0a_map’ defined but not used
[-Wunused-const-variable=]
static const struct parent_map gcc_xo_gpll6_gpll0a_map[] = {
^~~~~~~~~~~~~~~~~~~~~~~
drivers/clk/qcom/gcc-msm8939.c:598:32: warning: ‘gcc_xo_gpll6_gpll0_map’
defined but not used [-Wunused-const-variable=]
static const struct parent_map gcc_xo_gpll6_gpll0_map[] = {
^~~~~~~~~~~~~~~~~~~~~~
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Jason Yan <yanaijie@huawei.com>
Link: https://lore.kernel.org/r/20200911013722.1459387-1-yanaijie@huawei.com
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This addresses the following sparse warning:
drivers/clk/qcom/gcc-ipq8074.c:4325:17: warning: symbol
'pcie0_rchng_clk_src' was not declared. Should it be static?
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Jason Yan <yanaijie@huawei.com>
Link: https://lore.kernel.org/r/20200921142750.875142-1-yanaijie@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
support CLK_OF_DECLARE and builtin_platform_driver_probe
double clk init method.
add module author, description and license to support building
Soc Rk3399 clock driver as module.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200914022316.24045-1-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers.
use CONFIG_CLK_RKXX for Rk soc clk driver.
Mark CONFIG_CLK_RK3399 to "tristate",
to support building Rk3399 SoC clock driver as module.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200914022304.23908-1-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200914022225.23613-5-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module..
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200914022225.23613-4-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module..
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200914022225.23613-3-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The parent names 'mux_timer_src_p' is not used:
In file included from drivers/clk/rockchip/clk-rk3308.c:13:0:
drivers/clk/rockchip/clk-rk3308.c:136:7: warning: ‘mux_timer_src_p’ defined but not used [-Wunused-const-variable=]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200916161740.14173-6-krzk@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
As i.MX21 support has been removed, get rid of its clock driver too.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Allwinner A100 SoC, and adding support for the sigma-delta modulation on
the audio PLL for the R40.
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Merge tag 'sunxi-clk-for-5.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver updates from Maxime Ripard:
Our usual PR for the Allwinner SoCs, this time adding support for the
Allwinner A100 SoC, and adding support for the sigma-delta modulation on
the audio PLL for the R40.
* tag 'sunxi-clk-for-5.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL
clk: sunxi-ng: add support for the Allwinner A100 CCU
dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU
- Add support for the new R-Car V3U (R8A779A0) SoC,
- Minor fixes and improvements.
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Merge tag 'clk-renesas-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the new R-Car V3U (R8A779A0) SoC
- Add support for the VSP for Resizing clock on RZ/G1H,
- Fix VSP clock names to match corrected hardware documentation.
- Minor fixes and improvements
* tag 'clk-renesas-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: rcar-gen3: Update description for RZ/G2
clk: renesas: cpg-mssr: Add support for R-Car V3U
clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv
clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0
dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions
dt-bindings: power: Add r8a779a0 SYSC power domain definitions
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
clk: renesas: r8a7742: Add clk entry for VSPR
The rcar-gen3-cpg driver is also used on Renesas RZ/G2 SoC's, update the
description for the CLK_RCAR_GEN3_CPG config symbol to reflect this.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Link: https://lore.kernel.org/r/20200911101703.20521-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Initial support for R-Car V3U (r8a779a0), including core, module
clocks, resets, and register access, because register specification
differs from R-Car Gen2/3.
Inspired by patches in the BSP by LUU HOAI.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1599810232-29035-4-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Clock and Power Domain definitions for the Renesas R-Car V3U (R8A779A0)
SoC, shared by driver and DT source files.
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Merge tag 'renesas-r8a779a0-dt-binding-defs-tag' into clk-renesas-for-v5.10
Renesas R-Car V3U DT Binding Definitions
Clock and Power Domain definitions for the Renesas R-Car V3U (R8A779A0)
SoC, shared by driver and DT source files.
To support other register layouts in the future, add register pointers
of {control,status,reset,reset_clear}_regs into struct cpg_mssr_priv.
After that, we can remove unused macros like MSTPSR(). No behavioral
changes.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1599810232-29035-3-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
For the CPU clock registration two parent clocks are required, these
are now being passed as struct clk_hw pointers, rather than by the
global scope names. That allows us to avoid __clk_lookup() calls
and simplifies a bit the CPU clock registration function.
While at it drop unneeded extern keyword in the function declaration.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20200826171529.23618-3-s.nawrocki@samsung.com
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Use non-zero clock IDs in definitions of the CPU parent clocks
for exynos5420, exynos5250 SoCs. This will allow us to reference
the parent clocks directly in the driver by cached struct clk_hw
pointers, rather than doing clk lookup by name.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20200826171529.23618-2-s.nawrocki@samsung.com
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Add clock ID definitions for the CPU parent clocks for SoCs
which don't have such definitions yet. This will allow us to
reference the parent clocks directly by cached struct clk_hw
pointers in the clock provider, rather than doing clk lookup
by name.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200826171529.23618-1-s.nawrocki@samsung.com
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds a clk ID to the mout_sw_aclk_g3d clk definition so related
clk pointer gets cached in the driver's private data and can be used
later instead of a __clk_lookup() call.
With that we have all clocks used in the clk_prepare_enable() calls in the
clk provider init callback cached in clk_data.hws[] and we can reference
the clk pointers directly rather than using __clk_lookup() with global names.
Link: https://lore.kernel.org/r/20200811151251.31613-2-s.nawrocki@samsung.com
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds ID for the mout_sw_aclk_g3d (SW_CLKMUX_ACLK_G3D) clock,
mostly for internal use in the CMU driver. It will allow to avoid the
__clk_lookup() call when setting up the clock during the clock provider
initialization.
Link: https://lore.kernel.org/r/20200811151251.31613-1-s.nawrocki@samsung.com
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
BPLL clock must not be disabled because it is needed for proper DRAM
operation. This is normally handled by respective memory devfreq driver,
but when that driver is not yet probed or its probe has been deferred
the clock might get disabled what causes board hang. Fix this by calling
clk_prepare_enable() directly from the clock provider driver.
Cc: stable@vger.kernel.org
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Lukasz Luba <lukasz.luba@arm.com>
Tested-by: Lukasz Luba <lukasz.luba@arm.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200807133143.22748-1-m.szyprowski@samsung.com
Fixes: 6e7674c3c6 ("memory: Add DMC driver for Exynos5422")
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
A few words were misspelled in this comment.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the necessary bits so unnecessary amlogic clock controllers can be
compiled out. This allows to save a few kB when necessary.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200828154735.435374-1-jbrunet@baylibre.com
Fix and add missing kerneldoc to fix compile warnings like:
drivers/clk/imx/clk-pfd.c:27: warning: Function parameter or member 'hw' not described in 'clk_pfd'
drivers/clk/imx/clk-pllv3.c:53: warning: Function parameter or member 'ref_clock' not described in 'clk_pllv3'
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
According to RM, Page 574, Chapter 5.2.6.4.3 Peripheral clock slice,
"IP clock slices must be stopped to change the clock source.".
So we must have CLK_SET_PARENT_GATE flag to avoid glitch.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
According to RM, for peripheral clock slice,
"IP clock slices must be stopped to change the clock source.".
So we must have CLK_SET_PARENT_GATE flag to avoid glitch.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
VSP1 instances VSPS (which stands for "VSP Standard") and VSPR (which
stands for "VSP for Resizing") were wrongly named as "vsp1-sy" and
"vsp1-rt". The clock section in the SoC datasheets misunderstood the
abbreviations as meaning VSP System and VSP Realtime, and named the
corresponding clocks VSP1(SY) and VSP1(RT). This mistake has been
carried over to the kernel code.
This patch fixes this by renaming the clock names to "vsps" and "vspr".
Inspired from commit 79ea9934b8 ("ARM: shmobile: r8a7790: Rename
VSP1_(SY|RT) clocks to VSP1_(S|R)")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20200831183722.8165-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add clock entry 130 for VSPR (VSP for Resizing) module, so that this module
can be used on R8A7742 (RZ/G1H) SoC.
Alongside rename clock entry "vsp1-sy" to "vsps" (VSP Standard), so that
VSP1 clock names are in sync.
Note: The entry for VSPR clock was accidentally dropped from RZ/G manual
when all the information related to RT were removed.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200831180312.7453-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The root clock slice at offset 0xbf80 should be memrepair
clock, so correct it. And this clock should be always on
to make sure the memory repair function can works well.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The root clock slice at 0xbf00 is media_ldb clock,
not csi_phy2_ref, so correct it.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On Amlogic Meson G12b platform, similar to fclk_div3, the fclk_div2
seems to be necessary for the system to operate correctly as well.
Typically, the clock also gets chosen by the eMMC peripheral. This
probably masked the problem so far. However, when booting from a SD
card the clock seems to get disabled which leads to a system freeze.
Let's mark this clock as critical, fixing boot from SD card on G12b
platforms.
Fixes: 085a4ea93d ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/577e0129e8ee93972d92f13187ff4e4286182f67.1598629915.git.stefan@agner.ch
