Commit Graph

12 Commits

Author SHA1 Message Date
Jon Mason
5aeda7bf8a ARM: dts: NSP: Add and enable amac2
Add and enable the third AMAC ethernet interface in the device trees for
the platforms where it is present.  Also, enable amac1 on some of the
platforms where that was missing.

Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2017-01-18 17:18:21 -08:00
Jon Mason
d9ff8878bb ARM: dts: NSP: Add BCM958625K switch ports
Add the layout of the switch ports found on the BCM958625K reference
board. The CPU port is hooked up to the AMAC0 Ethernet controller
adapter.

Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2017-01-18 17:18:20 -08:00
Jon Mason
fe6bf99997 ARM: dts: NSP: Correct NAND partition unit address
The NAND partition unit address does not match the other NSP device tree
files.  This change makes them uniform.

Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2017-01-18 17:18:18 -08:00
Jon Mason
1fd2bb6ceb ARM: dts: NSP: DT Clean-ups
The QSPI entry was added out of the sequental order that the rest of the
DTSI file is in.  Move it to make it fit in properly.  Also, some other
entries have been added in a non-alphabetical order in the DTS files,
making them different from the other NSP DTS files.  Move the relevant
peices to make it match.  Finally, remove errant new lines.

Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2017-01-18 17:18:17 -08:00
Kamal Dasu
329f98c197 ARM: dts: NSP: Add QSPI nodes to NSPI and bcm958625k DTSes
Adding QSPI Device Tree node compatible with the new spi-bcm-qspi driver for
the Broadcom Northstar Plus SoC DTSI and bcm958625k reference board.

Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-10-19 06:40:43 -07:00
Jon Mason
21af8f4546 ARM: dts: NSP: Specify RAM amount for BCM958625K board
Add 2GB of memory starting at physical offset 0x6000_0000.

Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-08-08 18:41:22 -07:00
Jon Mason
13d04f2093 ARM: dts: NSP: Add AMAC entries
Add Device Tree entries for the Ethernet devices (AMAC) present on the Broadcom
Northstar Plus SoCs.

Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-08-08 11:06:26 -07:00
Yendapally Reddy Dhananjaya Reddy
8dbcad020f ARM: dts: nsp: Add sata device tree entry
Add sata support to the Northstar Plus SoC device tree.

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2016-06-16 16:24:55 -04:00
Yendapally Reddy Dhananjaya Reddy
ea2d8975e3 ARM: dts: enable pinctrl for Broadcom NSP
This enables the pinctrl support for Broadcom NSP SoC

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yrdreddy@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-12-06 19:45:19 -08:00
Jon Mason
41254754aa ARM: dts: NSP: Add NAND Support to DT
Add NAND support to the device tree for the Broadcom Northstar Plus SoC.
Since no driver changes are needed to enable this hardware, only the
device tree changes are required to make this functional.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-11-16 10:48:54 -08:00
Jon Mason
1dbcfb228b ARM: dts: NSP: Add PCI support
Add PCI support to the Northstar Plus SoC.  This uses the existing
pcie-iproc driver.  So, all that is needed is device tree entries in the
DTS.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-11-16 10:48:53 -08:00
Jon Mason
7b2e987de2 ARM: NSP: add minimal Northstar Plus device tree
Add a very minimalistic set of Northstar Plus Device Tree files which
describes the SoC and the BCM958625 implementation.  The perpherials
described are:

ARM Cortex A9 CPU
2 8250 UARTs
ARM GIC
PL310 L2 Cache
ARM A9 Global timer

Signed-off-by: Kapil Hali <kapilh@broadcom.com>
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-09-14 15:48:02 -07:00