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7232 Commits

Author SHA1 Message Date
Claudiu Beznea
fcedb589b5 clk: at91: sam9x60: support only two programmable clocks 
According to datasheet (Chapter 29.16.13, PMC Programmable Clock Register)
there are only two programmable clocks on SAM9X60.

Fixes: 01e2113de9 ("clk: at91: add sam9x60 pmc driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1602686072-28296-1-git-send-email-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-14 10:06:52 -07:00
Paul Cercueil
1a3c4dd4e1 clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate 
Clocks that don't have a divider are in our case all marked with the
CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation
should modify the value pointed to by parent_rate, in order to propagate
the rate change to the parent, as explained in the documentation of
clk_set_rate().

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-5-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 20:04:50 -07:00
Paul Cercueil
2e4ee634f8 clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT 
The custom clocks have custom functions to round, get or set their rate.
Therefore, we can't assume that they need the CLK_SET_RATE_PARENT flag.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-4-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 20:04:50 -07:00
Paul Cercueil
3860dc599b clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL 
CLK_SET_RATE_GATE means that the clock must be gated when being
reclocked. This is not the case for the PLLs in Ingenic SoCs.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-3-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 20:04:50 -07:00
Paul Cercueil
21534fe39c clk: ingenic: Use readl_poll_timeout instead of custom loop 
Use the readl_poll_timeout() function instead of rolling our own
busy-wait loops. This makes the code simpler.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-2-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 20:04:50 -07:00
Paul Cercueil
29c37341b5 clk: ingenic: Use to_clk_info() macro for all clocks 
The to_clk_info() previously had a BUG_ON() to check that it was only
called for PLL clocks. Yet, all the other clocks were doing the exact
same thing the macro does, in-line.

Move the to_clk_info() macro to the top of the file, remove the
hardcoded BUG_ON(), and use it everywhere it makes sense.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 20:04:50 -07:00
Navid Emamdoost
f6c992ca7d clk: bcm2835: add missing release if devm_clk_hw_register fails 
In the implementation of bcm2835_register_pll(), the allocated pll is
leaked if devm_clk_hw_register() fails to register hw. Release pll if
devm_clk_hw_register() fails.

Signed-off-by: Navid Emamdoost <navid.emamdoost@gmail.com>
Link: https://lore.kernel.org/r/20200809231202.15811-1-navid.emamdoost@gmail.com
Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the audio domain clocks")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 20:02:39 -07:00
Claudiu Beznea
c6968ac08d clk: at91: clk-sam9x60-pll: remove unused variable 
Fix variable set but not used compilation warning.

Fixes: 43b1bb4a9b ("clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1598338751-20607-4-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 19:59:01 -07:00
Claudiu Beznea
85d071e7f1 clk: at91: clk-main: update key before writing AT91_CKGR_MOR 
SAMA5D2 datasheet specifies on chapter 33.22.8 (PMC Clock Generator
Main Oscillator Register) that writing any value other than
0x37 on KEY field aborts the write operation. Use the key when
selecting main clock parent.

Fixes: 27cb1c2083 ("clk: at91: rework main clk implementation")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/1598338751-20607-3-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 19:59:01 -07:00
Claudiu Beznea
eddfb2e1ee clk: at91: remove the checking of parent_name 
There is no need to check parent_name variable while assigning it to
init.parent_names. parent_name variable is already checked at
the beginning of at91_clk_register_peripheral() function.

Fixes: 6114067e43 ("clk: at91: add PMC peripheral clocks")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/1598338751-20607-2-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 19:59:01 -07:00
Xu Wang
eff06bd5e5 clk: clk-prima2: fix return value check in prima2_clk_init() 
In case of error, the function clk_register() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().

Signed-off-by: Xu Wang <vulab@iscas.ac.cn>
Link: https://lore.kernel.org/r/20200921034522.9077-1-vulab@iscas.ac.cn
Acked-by: Barry Song <baohua@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 19:54:30 -07:00
Lubomir Rintel
07c565b42a clk: mmp2: Fix the display clock divider base 
The LCD clock dividers are apparently based on one. No datasheet,
determined empirically, but seems to be confirmed by line 19 of lcd.fth in
OLPC laptop's Open Firmware [1]:

   h# 00000700 value pmua-disp-clk-sel  \ PLL1 / 7 -> 113.86 MHz

[1] https://raw.githubusercontent.com/quozl/openfirmware/65a08a73b2cac/cpu/arm/olpc/lcd.fth

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lore.kernel.org/r/20200925233914.227786-1-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 19:53:36 -07:00
Rikard Falkeborn
6487649ee8 clk: pxa: Constify static struct clk_ops 
Constify a couple of static struct clk_ops that are not modified. Their
only usage is inside the macros and their address is passed to
clk_register_composite() which takes pointers to const struct clk_ops.
This allows the compiler to put them in read-only memory.

Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20200922184715.1854-1-rikard.falkeborn@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 19:49:11 -07:00
Serge Semin
9ba9ad8f5b clk: baikal-t1: Mark Ethernet PLL as critical 
We've discovered that disabling the so called Ethernet PLL causes reset of
the devices consuming its outgoing clock. The resets happen automatically
even if each underlying clock gate is turned off. Due to that we can't
disable the Ethernet PLL until the kernel is prepared for the corresponding
resets. So for now just mark the PLL clock provider as critical.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: linux-mips@vger.kernel.org
Link: https://lore.kernel.org/r/20200920110335.18034-1-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 19:48:34 -07:00
Zhao Qiang
e9501b975a clk: qoriq: modify MAX_PLL_DIV to 32 
On LS2088A, Watchdog need clk divided by 32,
so modify MAX_PLL_DIV to 32

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Link: https://lore.kernel.org/r/20200916030311.17280-1-qiang.zhao@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 19:48:09 -07:00
Lars-Peter Clausen
a3947209d3 clk: axi-clkgen: Set power bits for fractional mode 
Using the fractional dividers requires some additional power bits to be
set.

The fractional power bits are not documented and the current heuristic
for setting them seems be insufficient for some cases. Just always set all
the fractional power bits when in fractional mode.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20201001085948.21412-2-alexandru.ardelean@analog.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 19:44:40 -07:00
Lars-Peter Clausen
86378cf646 clk: axi-clkgen: Add support for fractional dividers 
The axi-clkgen has (optional) fractional dividers on the output clock
divider and feedback clock divider path. Utilizing the fractional dividers
allows for a better resolution of the output clock, being able to
synthesize more frequencies.

Rework the driver support to support the fractional register fields, both
for setting a new rate as well as reading back the current rate from the
hardware.

For setting the rate if no perfect divider settings were found in
non-fractional mode try again in fractional mode and see if better settings
can be found. This appears to be the recommended mode of operation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 19:44:40 -07:00
Jonathan Marek
80a18f4a85 clk: qcom: Add display clock controller driver for SM8150 and SM8250 
Add support for the display clock controller found on SM8150 and SM8250.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250)
Link: https://lore.kernel.org/r/20200927190653.13876-3-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 18:18:06 -07:00
Jonathan Marek
0e94711a1f clk: qcom: add video clock controller driver for SM8250 
Add support for the video clock controller found on SM8250 based devices.

Derived from the downstream driver.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20200923160635.28370-6-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 18:05:04 -07:00
Jonathan Marek
5658e8cf1a clk: qcom: add video clock controller driver for SM8150 
Add support for the video clock controller found on SM8150 based devices.

Derived from the downstream driver.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20200923160635.28370-5-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 18:05:04 -07:00
Konrad Dybcio
8c18b41b39 clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs 
This change adds GDSCs, resets and most of the missing
clocks to the msm8994 GCC driver. The remaining ones
are of local_vote_clk and gate_clk type, which are not
yet supported upstream. Also reorder them to match the
original downstream driver.

Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20201005145855.149206-1-konradybcio@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 18:04:36 -07:00
Julia Lawall
3270ee1455 clk: meson: use semicolons rather than commas to separate statements 
Replace commas with semicolons.  What is done is essentially described by
the following Coccinelle semantic patch (http://coccinelle.lip6.fr/):

// <smpl>
@@ expression e1,e2; @@
e1
-,
+;
e2
... when any
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Link: https://lore.kernel.org/r/1601233948-11629-11-git-send-email-Julia.Lawall@inria.fr
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 17:43:07 -07:00
Julia Lawall
39443a27cb clk: mvebu: ap80x-cpu: use semicolons rather than commas to separate statements 
Replace commas with semicolons.  What is done is essentially described by
the following Coccinelle semantic patch (http://coccinelle.lip6.fr/):

// <smpl>
@@ expression e1,e2; @@
e1
-,
+;
e2
... when any
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Link: https://lore.kernel.org/r/1601233948-11629-10-git-send-email-Julia.Lawall@inria.fr
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 17:43:05 -07:00
Julia Lawall
4f8a13e1c2 clk: uniphier: use semicolons rather than commas to separate statements 
Replace commas with semicolons.  What is done is essentially described by
the following Coccinelle semantic patch (http://coccinelle.lip6.fr/):

// <smpl>
@@ expression e1,e2; @@
e1
-,
+;
e2
... when any
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Link: https://lore.kernel.org/r/1601233948-11629-2-git-send-email-Julia.Lawall@inria.fr
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 17:43:03 -07:00
Wang Qing
1843dff668 clk/qcom: fix spelling typo 
Modify the comment typo: "compliment" -> "complement".

Signed-off-by: Wang Qing <wangqing@vivo.com>
Link: https://lore.kernel.org/r/1600930506-394-1-git-send-email-wangqing@vivo.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 16:32:27 -07:00
Fabien Parent
a682248321 clk: mediatek: Add MT8167 clock support 
Add the following clock support for MT8167 SoC: topckgen, apmixedsys,
infracfg, audsys, imgsys, mfgcfg, vdecsys.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20200918132303.2831815-2-fparent@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-13 15:46:01 -07:00
Hanks Chen
804a892456 clk: mediatek: add UART0 clock support 
Add MT6779 UART0 clock support.

Fixes: 710774e048 ("clk: mediatek: Add MT6779 clock support")
Signed-off-by: Wendell Lin <wendell.lin@mediatek.com>
Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-08 14:45:16 -07:00
Stephen Boyd
b608f11d49 clk: rockchip: Initialize hw to error to avoid undefined behavior 
We can get down to this return value from ERR_CAST() without
initializing hw. Set it to -ENOMEM so that we always return something
sane.

Fixes the following smatch warning:

drivers/clk/rockchip/clk-half-divider.c:228 rockchip_clk_register_halfdiv() error: uninitialized symbol 'hw'.
drivers/clk/rockchip/clk-half-divider.c:228 rockchip_clk_register_halfdiv() warn: passing zero to 'ERR_CAST'

Cc: Elaine Zhang <zhangqing@rock-chips.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Fixes: 956060a527 ("clk: rockchip: add support for half divider")
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-10-07 19:08:38 -07:00
Olof Johansson
accdab6d9e Merge tag 'imx-soc-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/soc 
i.MX SoC update for 5.10:

- A series from Fabio Estevam to remove legacy non-DT i.MX platforms
  support and related board files. This is a natural move, as the
  platforms had been converted to DT for years, and we have not seen
  any users around these legacy non-DT support for a while.
- Enable cpufreq support for i.MX7ULP platform.

* tag 'imx-soc-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (26 commits)
  clk: imx: imx35: Remove mx35_clocks_init()
  clk: imx: imx31: Remove mx31_clocks_init()
  clk: imx: imx27: Remove mx27_clocks_init()
  ARM: imx: Remove unused definitions
  ARM: imx35: Retrieve the IIM base address from devicetree
  ARM: imx3: Retrieve the AVIC base address from devicetree
  ARM: imx3: Retrieve the CCM base address from devicetree
  ARM: imx31: Retrieve the IIM base address from devicetree
  ARM: imx27: Retrieve the CCM base address from devicetree
  ARM: imx27: Retrieve the SYSCTRL base address from devicetree
  ARM: imx: Remove remnant board file support pieces
  ARM: imx: Remove imx device directory
  ARM: imx: Remove iomux-v3 board code
  ARM: imx3: Remove imx3 soc_init()
  ARM: imx31: Remove remaining i.MX31 board code
  ARM: imx27: Retrieve AVIC base address from devicetree
  ARM: imx27: Get rid of mm-imx27.c
  ARM: imx27: Remove iomux-v1 board code
  ARM: imx27: Remove imx27_soc_init()
  ARM: imx7ulp: enable cpufreq
  ...

Link: https://lore.kernel.org/r/20200923073009.23678-2-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
 2020-10-03 13:16:50 -07:00
Stephen Boyd
f102ed0686 clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate() 
The provider variable is already dereferenced earlier in this function.
Drop the check for NULL as it is impossible.

Found with smatch

drivers/clk/tegra/clk-tegra210-emc.c:131 tegra210_clk_emc_set_rate() warn: variable dereferenced before check 'provider' (see line 124)

Cc: Joseph Lo <josephl@nvidia.com>
Cc: Thierry Reding <treding@nvidia.com>
Fixes: 0ac65fc946 ("clk: tegra: Implement Tegra210 EMC clock")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200922191641.2305144-1-sboyd@kernel.org
Acked-by: Thierry Reding <treding@nvidia.com>
 2020-09-23 16:59:28 -07:00
Tero Kristo
6045124ebe clk: ti: dra7: add missing clkctrl register for SHA2 instance 
DRA7 SoC has two SHA instances. Add the clkctrl entry for the second
one.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Link: https://lore.kernel.org/r/20200907082600.454-4-t-kristo@ti.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 13:00:07 -07:00
Tero Kristo
b7a7943fe2 clk: ti: clockdomain: fix static checker warning 
Fix a memory leak induced by not calling clk_put after doing of_clk_get.

Reported-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Link: https://lore.kernel.org/r/20200907082600.454-3-t-kristo@ti.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 13:00:07 -07:00
Tero Kristo
cec4a609a8 clk: ti: autoidle: add checks against NULL pointer reference 
The clk pointer passed to omap2_clk_(deny|allow)_idle can be NULL, so
add checks for this.

Reported-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Link: https://lore.kernel.org/r/20200907082600.454-2-t-kristo@ti.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 13:00:07 -07:00
Tero Kristo
4630ef134e clk: keystone: sci-clk: add 10% slack to set_rate 
Currently, we request exact clock rates from the firmware to be set with
set_rate. Due to some rounding errors and internal functionality of the
firmware itself, this can fail. Thus, add some slack to the set_rate
functionality so that we are always guaranteed to pass. The firmware
always attempts to use frequency as close to the target freq as
possible despite the slack given here.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Link: https://lore.kernel.org/r/20200907085740.1083-4-t-kristo@ti.com
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:58:52 -07:00
Tero Kristo
d3f3f499cb clk: keystone: sci-clk: cache results of last query rate operation 
Cache results of the latest query rate operation. This optimizes the
firmware interface a bit, avoiding unnecessary calls to firmware if we
know the result already; the firmware interface is pretty expensive
to use for query rate functionality.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Link: https://lore.kernel.org/r/20200907085740.1083-3-t-kristo@ti.com
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:58:43 -07:00
Tero Kristo
2f05cced73 clk: keystone: sci-clk: fix parsing assigned-clock data during probe 
The DT clock probe loop incorrectly terminates after processing "clocks"
only, fix this by re-starting the loop when all entries for current
DT property have been parsed.

Fixes: 8e48b33f9d ("clk: keystone: sci-clk: probe clocks from DT instead of firmware")
Reported-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Link: https://lore.kernel.org/r/20200907085740.1083-2-t-kristo@ti.com
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:58:34 -07:00
Zou Wei
a2618360ab clk: mediatek: fix platform_no_drv_owner.cocci warnings 
./drivers/clk/mediatek/clk-mt6765.c:912:3-8: No need to set .owner here. The core will do it.

 Remove .owner field if calls are used which set it automatically

Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci

Fixes: 1aca9939bf ("clk: mediatek: Add MT6765 clock support")
Signed-off-by: Zou Wei <zou_wei@huawei.com>
Link: https://lore.kernel.org/r/1600761065-71353-1-git-send-email-zou_wei@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:56:59 -07:00
Liu Shixin
b37c1e673e clk: mediatek: mt7629: simplify the return expression of mtk_infrasys_init 
Simplify the return expression.

Signed-off-by: Liu Shixin <liushixin2@huawei.com>
Link: https://lore.kernel.org/r/20200921082426.2591042-1-liushixin2@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:56:37 -07:00
Liu Shixin
eff8a85acf clk: mediatek: mt6797: simplify the return expression of mtk_infrasys_init 
Simplify the return expression.

Signed-off-by: Liu Shixin <liushixin2@huawei.com>
Link: https://lore.kernel.org/r/20200921082425.2590990-1-liushixin2@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:56:26 -07:00
Dinh Nguyen
b02cf0c473 clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clk 
The fixed divider the emac_ptp_free_clk should be 2, not 4.

Fixes: 07afb8db73 ("clk: socfpga: stratix10: add clock driver for
Stratix10 platform")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20200831202657.8224-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:54:41 -07:00
YueHaibing
b10f224935 clk: socfpga: agilex: Remove unused variable 'cntr_mux' 
drivers/clk/socfpga/clk-agilex.c:24:37: warning: ‘cntr_mux’ defined but not used [-Wunused-const-variable=]
 static const struct clk_parent_data cntr_mux[] = {
                                     ^~~~~~~~

There is no caller in tree, so can remove it.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lore.kernel.org/r/20200915020950.4688-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:46:12 -07:00
Krzysztof Kozlowski
84afc9ecf4 clk: si5341: drop unused 'err' variable 
'err' is assigned but never read:

  /drivers/clk/clk-si5341.c: In function ‘si5341_output_get_parent’:
  drivers/clk/clk-si5341.c:886:6: warning: variable ‘err’ set but not used [-Wunused-but-set-variable]

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200916161740.14173-5-krzk@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:44:41 -07:00
Krzysztof Kozlowski
f5e75b4aae clk: mmp: pxa1928: drop unused 'clk' variable 
'clk' is assigned but never read:

  drivers/clk/mmp/clk-of-pxa1928.c: In function ‘pxa1928_pll_init’:
  drivers/clk/mmp/clk-of-pxa1928.c:71:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable]

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200916161740.14173-4-krzk@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:44:40 -07:00
Krzysztof Kozlowski
425c23d382 clk: at91: drop unused at91sam9g45_pcr_layout 
The at91sam9g45_pcr_layout is not used so drop it to fix build warning:

  drivers/clk/at91/at91sam9g45.c:49:36: warning:
    'at91sam9g45_pcr_layout' defined but not used [-Wunused-const-variable=]

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20200916161740.14173-1-krzk@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:44:35 -07:00
Krzysztof Kozlowski
faeda014b4 clk: davinci: add missing kerneldoc 
Add missing kerneldoc to fix compile warning:

  drivers/clk/davinci/da8xx-cfgchip.c:578: warning: Function parameter or member 'dev' not described in 'da8xx_cfgchip_register_usb1_clk48'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: David Lechner <david@lechnology.com>
Link: https://lore.kernel.org/r/20200916161740.14173-3-krzk@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:44:16 -07:00
Krzysztof Kozlowski
52ba4fa40f clk: fixed: add missing kerneldoc 
Add missing kerneldoc to fix compile warnings like:

  drivers/clk/clk-fixed-factor.c:211: warning: Function parameter or member 'node' not described in 'of_fixed_factor_clk_setup'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200916161740.14173-2-krzk@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:44:14 -07:00
Krzysztof Kozlowski
533852d718 clk: s2mps11: initialize driver via module_platform_driver 
The driver was using subsys_initcall() because in old times deferred
probe was not supported everywhere and specific ordering was needed.
Since probe deferral works fine and specific ordering is discouraged
(hides dependencies between drivers and couples their boot order), the
driver can be converted to regular module_platform_driver.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200921203558.19554-1-krzk@kernel.org
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:30:52 -07:00
Hoegeun Kwon
4ceb4b6bd2 clk: bcm: rpi: Add register to control pixel bvb clk 
To use QHD or higher, we need to modify the pixel_bvb_clk value. So
add register to control this clock.

Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Link: https://lore.kernel.org/r/20200901040759.29992-2-hoegeun.kwon@samsung.com
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:29:17 -07:00
Marek Szyprowski
f3bb0f796f clk: samsung: exynos4: mark 'chipid' clock as CLK_IGNORE_UNUSED 
The ChipID IO region has it's own clock, which is being disabled while
scanning for unused clocks. It turned out that some CPU hotplug, CPU idle
or even SOC firmware code depends on the reads from that area. Fix the
mysterious hang caused by entering deep CPU idle state by ignoring the
'chipid' clock during unused clocks scan, as there are no direct clients
for it which will keep it enabled.

Fixes: e062b57177 ("clk: exynos4: register clocks using common clock framework")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20200922124046.10496-1-m.szyprowski@samsung.com
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:26:59 -07:00
Stephen Boyd
51644df867 Merge tag 'for-5.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-fixes 
Pull Tegra clk driver fixes from Thierry Reding:

This is a set of small fixes for the Tegra clock driver.

* tag 'for-5.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: Fix missing prototype for tegra210_clk_register_emc()
  clk: tegra: Always program PLL_E when enabled
  clk: tegra: Capitalization fixes
 2020-09-22 12:09:07 -07:00