Ben Skeggs
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9d6ba0b58c
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drm/nvc0/pm: very initial mclk freq change
Loads of magic missing, this will probably blow up if you try it.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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2012-05-24 16:31:34 +10:00 |
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Ben Skeggs
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6b91d6b056
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drm/nvc0/pm: enable mpll src pll, and calc mpll coefficients
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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2012-05-24 16:31:30 +10:00 |
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Ben Skeggs
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a1da205f42
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drm/nvc0/pm: start filling in memory reclocking stubs
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2012-05-24 16:31:29 +10:00 |
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Ben Skeggs
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1ae73f2f16
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drm/nvc0/pm: restrict pll mode to clocks that can actually use it
Fixes reclocking failure on some chips where we attempted to set PDAEMON
to PLL mode.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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2012-03-13 17:14:58 +10:00 |
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Ben Skeggs
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045da4e555
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drm/nvc0/pm: initial engine reclocking
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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2011-12-21 19:01:46 +10:00 |
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Ben Skeggs
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8ce51fcfee
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drm/nvc0/pm: minor clock readback fixes
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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2011-09-20 16:11:55 +10:00 |
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Ben Skeggs
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9698b9a680
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drm/nvc0/pm: more complete parsing of clock domains
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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2011-09-20 16:03:34 +10:00 |
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Ben Skeggs
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354d0781e5
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drm/nvc0/pm: initial implementation of clocks_get()
Not too certain on memory clock yet, but it gets the right numbers for
each perflvl on my NVC0.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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2011-09-20 16:03:16 +10:00 |
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