Commit Graph

137 Commits

Author SHA1 Message Date
Lennert Buytenhek
99c6dc117d [ARM] Feroceon: L2 cache support
This patch adds support for the unified Feroceon L2 cache controller
as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo
families of ARM SoCs.

Note that:

- Page table walks are outer uncacheable on Kirkwood and Discovery
  Duo, since the ARMv5 spec provides no way to indicate outer
  cacheability of page table walks (specifying it in TTBR[4:3] is
  an ARMv6+ feature).

  This requires adding L2 cache clean instructions to
  proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to
  tlbflush.h ({flush,clean}_pmd_entry()).  The latter case is handled
  by defining a new TLB type (TLB_FEROCEON) which is almost identical
  to the v4wbi one but provides a TLB_L2CLEAN_FR flag.

- The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2
  range by MVA' and 'invalidate L2 range by MVA') operations, and this
  patch uses those range operations for all Linux outer cache
  operations, as they are faster than the regular per-line operations.

  L2 range operations are not interruptible on this hardware, which
  avoids potential livelock issues, but can be bad for interrupt
  latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which
  allows you to select the maximum range size to operate on at once.
  (Valid range is between one cache line and one 4KiB page, and must
  be a multiple of the line size.)

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:04 +02:00
Lennert Buytenhek
777f9bebad [ARM] add Marvell Loki (88RC8480) SoC support
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.

This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:02 +02:00
Lennert Buytenhek
0ed1507183 [ARM] Feroceon: Feroceon-specific WA-cache compatible {copy,clear}_user_page()
This patch implements a set of Feroceon-specific
{copy,clear}_user_page() routines that perform more optimally than
the generic implementations.  This also deals with write-allocate
caches (Feroceon can run L1 D in WA mode) which otherwise prevents
Linux from booting.

[nico: optimized the code even further]

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Sylver Bruneau <sylver.bruneau@googlemail.com>
Tested-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-04-28 16:06:51 -04:00
Lennert Buytenhek
a7039bd6da [ARM] feroceon: remove CONFIG_CPU_DCACHE_WRITETHROUGH check
Since the Feroceon doesn't have a global WT override bit like
ARM926 does, remove all code relating to this mode of operation
from proc-feroceon.S.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-04-28 15:55:28 -04:00
Catalin Marinas
4a1fd556c1 [ARM] fix 48d7927bdf
The proc-*.S files have the _prefetch_abort pointer placed at the end
of the processor structure but the cpu-multi32.h defines it in the
second position. The patch also fixes the support for XSC3 and the
MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-04-24 10:06:45 +01:00
Russell King
d1964dab60 Merge branches 'arm', 'at91', 'ep93xx', 'iop', 'ks8695', 'misc', 'mxc', 'ns9x', 'orion', 'pxa', 'sa1100', 's3c' and 'sparsemem' into devel 2008-04-19 17:17:25 +01:00
Catalin Marinas
ba9279519b Allow the L2X0 outer cache support to be configurable
By default, this option was selected by the platform Kconfig. This
patch adds "depends on" to L2X0 so that it can be enabled/disabled
manually.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:17 +01:00
Bahadir Balban
bc02c58bd1 RealView: Add the configuration and build changes for PB1176
This patch enables the building of Linux for the PB1176 platform.

Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:16 +01:00
Bahadir Balban
78fdcb4287 RealView: Enable the configuration options for PB11MPCore
This patch adds the PB11MPCore support to the corresponding Kconfig
and Makefile to enable building.

Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:14 +01:00
Catalin Marinas
41267e208e RealView: Allow ARMv7 support for RealView/EB
This patch changes the CPU_V7 configuration dependency to allow
MACH_REALVIEW_EB.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:12 +01:00
Paul Brook
48d7927bdf Add a prefetch abort handler
This patch adds a prefetch abort handler similar to the data abort one
and renames the latter for consistency. Initial implementation by Paul
Brook with some renaming by Catalin Marinas.

Signed-off-by: Paul Brook <paul@codesourcery.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:07 +01:00
Catalin Marinas
d7f864be83 ARMv7: Add support for the ThumbEE state saving/restoring
This patch adds the detection and handling of the ThumbEE extension on
ARMv7 CPUs.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:06 +01:00
Lennert Buytenhek
9dd0b194bf Orion: orion -> orion5x rename
Do a global s/orion/orion5x/ of the Orion 5x-specific bits (i.e.
not the plat-orion bits.)

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Reviewed-by: Tzachi Perelstein <tzachi@marvell.com>
Acked-by: Saeed Bishara <saeed@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-03-27 14:51:41 -04:00
Russell King
c00d4ffdba Merge branch 'orion' into devel
* orion: (26 commits)
  [ARM] Orion: implement power-off method for QNAP TS-109/209
  [ARM] Orion: add support for QNAP TS-109/TS-209
  [ARM] Orion: I2C support
  [I2C] i2c-mv64xxx: Don't set i2c_adapter.retries
  [I2C] Split mv643xx I2C platform support
  [ARM] Orion: enable CONFIG_RTC_DRV_M41T80 for D-Link DNS-323
  [ARM] Orion defconfig
  [ARM] Orion: add support for Orion/MV88F5181 based D-Link DNS-323
  [ARM] Orion: MV88F5181 support bits
  [ARM] Orion: Buffalo/Revogear Kurobox Pro support
  [ARM] OrionNAS RD board support
  [ARM] Orion: support for Marvell Orion-2 (88F5281) Development Board
  [ARM] Orion: common platform setup for Gigabit Ethernet port
  [ARM] Orion: platform device registration for UART, USB and NAND
  [ARM] Orion: system timer support
  [ARM] Orion edge GPIO IRQ support
  [ARM] Orion: IRQ support
  [ARM] Orion: provide GPIO method for enabling hardware assisted blinking
  [ARM] Orion: GPIO support
  [ARM] Orion: programable address map support
  ...

Conflicts:

	arch/arm/Kconfig
	arch/arm/Makefile

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-01-28 13:21:30 +00:00
Russell King
d0d42df2a4 Merge branches 'at91', 'ep93xx', 'iop', 'kprobes', 'ks8695', 'misc', 'msm', 's3c2410', 'sa1100' and 'vfp' into devel
* at91: (24 commits)
  [ARM] 4615/4: sam926[13]ek buttons updated
  [ARM] 4765/1: [AT91] AT91CAP9A-DK board support
  [ARM] 4764/1: [AT91] AT91CAP9 core support
  [ARM] 4738/1: at91sam9261: Remove udc pullup enabling in board initialisation
  [ARM] 4761/1: [AT91] Board-support for NEW_LEDs
  [ARM] 4760/1: [AT91] SPI CS0 errata on AT91RM9200
  [ARM] 4759/1: [AT91] Buttons on CSB300
  [ARM] 4758/1: [AT91] LEDs
  [ARM] 4757/1: [AT91] UART initialization
  [ARM] 4756/1: [AT91] Makefile cleanup
  [ARM] 4755/1: [AT91] NAND update
  [ARM] 4754/1: [AT91] SSC library support
  [ARM] 4753/1: [AT91] Use DMA_BIT_MASK
  [ARM] 4752/1: [AT91] RTT, RTC and WDT peripherals on SAM9
  [ARM] 4751/1: [AT91] ISI peripheral on SAM9263
  [ARM] 4750/1: [AT91] STN LCD displays on SAM9261
  [ARM] 4734/1: at91sam9263ek: include IRQ for Ethernet PHY
  [ARM] 4646/1: AT91: configurable HZ, default to 128
  [ARM] 4688/1: at91: speed-up irq processing
  [ARM] 4657/1: AT91: Header definition update
  ...

* ep93xx:
  [ARM] 4671/1: ep93xx: remove obsolete gpio_line_* operations
  [ARM] 4670/1: ep93xx: implement IRQT_BOTHEDGE gpio irq sense type
  [ARM] 4669/1: ep93xx: simplify GPIO code and cleanups
  [ARM] 4668/1: ep93xx: implement new GPIO API

* iop:
  [ARM] 4770/1: GLAN Tank: correct physmap_flash_data width field
  [ARM] 4732/1: GLAN Tank: register rtc-rs5c372 i2c device
  [ARM] 4708/1: iop: update defconfigs for 2.6.24

* kprobes:
  ARM kprobes: let's enable it
  ARM kprobes: special hook for the kprobes breakpoint handler
  ARM kprobes: prevent some functions involved with kprobes from being probed
  ARM kprobes: don't let a single-stepped stmdb corrupt the exception stack
  ARM kprobes: add the kprobes hook to the page fault handler
  ARM kprobes: core code
  ARM kprobes: instruction single-stepping support

* ks8695:
  [ARM] 4603/1: KS8695: debugfs interface to view pin state
  [ARM] 4601/1: KS8695: PCI support

* misc:
  [ARM] remove duplicate includes
  [ARM] CONFIG_DEBUG_STACK_USAGE
  [ARM] 4689/1: small comment wrap fix
  [ARM] 4687/1: Trivial arch/arm/kernel/entry-common.S comment fix
  [ARM] 4666/1: ixp4xx: fix sparse warnings in include/asm-arm/arch-ixp4xx/io.h
  [ARM] remove reference to non-existent MTD_OBSOLETE_CHIPS
  [SERIAL] 21285: Report baud rate back via termios
  [ARM] Remove pointless casts from void pointers,
  [ARM] Misc minor interrupt handler cleanups
  [ARM] Remove at91_lcdc.h
  [ARM] ARRAY_SIZE() cleanup
  [ARM] Update mach-types

* msm:
  [ARM] msm: dma support for MSM7X00A
  [ARM] msm: board file for MACH_HALIBUT (QCT MSM7200A)
  [ARM] msm: irq and timer support for ARCH_MSM7X00A
  [ARM] msm: core platform support for ARCH_MSM7X00A

* s3c2410: (33 commits)
  [ARM] 4795/1: S3C244X: Add armclk and setparent call
  [ARM] 4794/1: S3C24XX: Comonise S3C2440 and S3C2442 clock code
  [ARM] 4793/1: S3C24XX: Add IRQ->GPIO pin mapping function
  [ARM] 4792/1: S3C24XX: Remove warnings from debug-macro.S
  [ARM] 4791/1: S3C2412: Make fclk a parent of msysclk
  [ARM] 4790/1: S3C2412: Fix parent selection for msysclk.
  [ARM] 4789/1: S3C2412: Add missing CLKDIVN register values
  [ARM] 4788/1: S3C24XX: Fix paramet to s3c2410_dma_ctrl if S3C2410_DMAF_AUTOSTART used.
  [ARM] 4787/1: S3C24XX: s3c2410_dma_request() should return the allocated channel number
  [ARM] 4786/1: S3C2412: Add SPI FIFO controll constants
  [ARM] 4785/1: S3C24XX: Add _SHIFT definitions for S3C2410_BANKCON registers
  [ARM] 4784/1: S3C24XX: Fix GPIO restore glitches
  [ARM] 4783/1: S3C24XX: Add s3c2410_gpio_getpull()
  [ARM] 4782/1: S3C24XX: Define FIQ_START for any FIQ users
  [ARM] 4781/1: S3C24XX: DMA suspend and resume support
  [ARM] 4780/1: S3C2412: Allow for seperate DMA channels for TX and RX
  [ARM] 4779/1: S3C2412: Add s3c2412_gpio_set_sleepcfg() call
  [ARM] 4778/1: S3C2412: Add armclk and init from DVS state
  [ARM] 4777/1: S3C24XX: Ensure clk_set_rate() checks the set_rate method for the clk
  [ARM] 4775/1: s3c2410: fix compilation error if only s3c2442 cpu is selected
  ...

* sa1100:
  [ARM] sa1100: add clock source support

* vfp:
  [ARM] 4584/2: ARMv7: Add Advanced SIMD (NEON) extension support
  [ARM] 4583/1: ARMv7: Add VFPv3 support
  [ARM] 4582/2: Add support for the common VFP subarchitecture
2008-01-28 13:21:21 +00:00
Tzachi Perelstein
d910a0aa21 [ARM] Feroceon: support old cores with ARM926 ID
This enables the usage of some old Feroceon cores
for which the CPU ID is equal to the ARM926 ID.
Relevant for Feroceon-1850 and old Feroceon-2850.

Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-01-26 15:03:41 +00:00
Assaf Hoffman
e50d64097b [ARM] Marvell Feroceon CPU core support
The Feroceon is a family of independent ARMv5TE compliant CPU core
implementations, supporting a variable depth pipeline and out-of-order
execution.  The Feroceon is configurable with VFP support, and the
later models in the series are superscalar with up to two instructions
per clock cycle.

This patch adds the initial low-level cache/TLB handling for this core.

Signed-off-by: Assaf Hoffman <hoffman@marvell.com>
Reviewed-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-01-26 15:03:38 +00:00
Andrew Victor
2b3b3516b6 [ARM] 4764/1: [AT91] AT91CAP9 core support
Add support for Atmel's AT91CAP9 Customizable Microcontroller family.
  <http://www.atmel.com/products/AT91CAP/Default.asp>

Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-01-26 15:01:13 +00:00
Brian Swetland
3042102a28 [ARM] msm: core platform support for ARCH_MSM7X00A
- core header files for arch-msm
- Kconfig and Makefiles to enable ARCH_MSM7X00A builds
- MSM7X00A specific arch_idle
- peripheral iomap and irq number definitions

Signed-off-by: Brian Swetland <swetland@google.com>
2008-01-26 14:39:14 +00:00
eric miao
2c8086a5d0 [ARM] pxa: PXA3xx base support
Signed-off-by: eric miao <eric.y.miao@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-15 18:53:43 +01:00
Russell King
fa0b62513b [ARM] pxa: Make CPU_XSCALE depend on PXA25x or PXA27x
PXA3 SoCs are supported by the Xscale3 CPU code rather than the
Xscale CPU code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-12 21:15:27 +01:00
Russell King
5957a4eb28 Merge branches 'at91', 'imx', 'iop', 'ixp', 'ks8695', 'misc', 'ns9xxx', 'pxa' and 's3c' into devel 2007-07-22 17:09:17 +01:00
Quinn Jensen
52c543f90c [ARM] 4461/1: MXC platform and i.MX31ADS core support
This patch adds the foundation pieces for
the Freescale MXC platforms, including
i.MX2 and i.MX3 based systems.

The bare-bones MX31 support in this patch
boots to the rootdev panic with 8250 serial
console configured "console=ttyS0,115200".
It assumes that Redboot is the boot loader.

Signed-off-by: Quinn Jensen <quinn.jensen@freescale.com>
Acked-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-07-22 15:44:46 +01:00
Catalin Marinas
11179d8ca2 [ARM] 4497/1: Only allow safe cache configurations on ARMv6 and later
Currently, Linux doesn't generate correct page tables for ARMv6 and
later cores if the cache policy is different from the default one (it
may lead to strongly ordered or shared device mappings). This patch
disallows cache policies other than writeback and the
CPU_[ID]CACHE_DISABLE options only affect the CP15 system control
register rather than the page tables.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-07-20 21:42:35 +01:00
Catalin Marinas
2eb8c82bc4 [ARM] 4503/1: nommu: Add noMMU support for ARMv7
This patch adds the necessary ifdef's to the proc-v7.S code and
defines the v7wbi_tlb_fns macro in pgtable-nommu.h

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-07-20 21:42:13 +01:00
Catalin Marinas
7092fc38ee [ARM] 4498/1: ARMv7: Remove the L2 cache configuration via the aux ctrl register
The auxiliary control and the L2 auxiliary control registers are
Cortex-A8 specific. They need to be removed from the generic ARMv7
support code.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-07-20 21:41:55 +01:00
Catalin Marinas
7b4c965a0b [ARM] 4504/1: nommu: Fix the ARMv6 support for MMU-less platforms
With this patch, Kconfig only selects CPU_HAS_ASID for the MMU
case. It also corrects the typo in the v6wbi_tlb_fns definition in
pgtable-nommu.h.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-07-20 21:29:56 +01:00
Catalin Marinas
367afaf83b [ARM] 4501/1: nommu: Select TLS register emulation if ARMv6 and not v6K
If not MMU and not v6K, access to the TLS register has to be
emulated. MMU-less systems do not provide a high page for kuser
helpers.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-07-20 21:29:48 +01:00
Catalin Marinas
2ccdd1e77d [ARM] 4394/1: ARMv7: Add the TLB range operations
We are currently using the ARMv6 operations but need to duplicate some
of the code because of the introduction of the new CPU barrier
instructions in ARMv7.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-30 14:32:07 +01:00
Russell King
516793c61b [ARM] ARMv6: add CPU_HAS_ASID configuration
Presently, we check for the minimum ARM architecture that we're
building for to determine whether we need ASID support.  This is
wrong - if we're going to support a range of CPUs which include
ARMv6 or higher, we need the ASID.

Convert the checks to use a new configuration symbol, and arrange
for ARMv6 and higher CPU entries to select it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-17 10:19:23 +01:00
Andrew Victor
c53c9cf60e [ARM] 4331/3: Support for Micrel/Kendin KS8695 processor
Add core support for the Kendin/Micrel KS8695 processor family.

It is an ARM922-T based SoC with integrated USART, 4-port Ethernet
Switch, WAN Ethernet port, and optional PCI Host bridge, etc.
 http://www.micrel.com/page.do?page=product-info/sys_on_chip.jsp

This patch is based on earlier patches from Lennert Buytenhek, Ben
Dooks and Greg Ungerer posted to the arm-linux-kernel mailing list in
March 2006;  and Micrel's 2.6.9 port.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-11 22:02:48 +01:00
Andrew Victor
877d7720f5 [ARM] 4370/3: AT91: Support for Atmel AT91SAM9RL processors.
Add support for Atmel's new AT91SAM9RL range of processors.
Includes similar peripherals as other AT91SAM9 processors, but with a
High-speed USB controller and various sizes of internal SRAM.

Signed-off-by: Nicolas Ferre <nicolas.ferre@rfo.atmel.com>
Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-11 21:07:54 +01:00
Kevin Hilman
7c6337e225 [ARM] 4303/3: base kernel support for TI DaVinci
Add base kernel support for the TI DaVinci platform.

This patch only includes interrupts, timers, CPU identification,
serial support and basic power and sleep controller init.  More
drivers to come.

Signed-off-by: Kevin Hilman <khilman@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-11 17:26:55 +01:00
Catalin Marinas
23688e999e [ARM] armv7: add Makefile and Kconfig entries
This patch adds the necessary lines to the Makefile and Kconfig files for
enabling the compilation of the ARMv7 CPU support.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-09 09:52:38 +01:00
Linus Torvalds
874ff01bd9 Merge git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial
* git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial: (25 commits)
  Documentation/kernel-docs.txt update.
  arch/cris: typo in KERN_INFO
  Storage class should be before const qualifier
  kernel/printk.c: comment fix
  update I/O sched Kconfig help texts - CFQ is now default, not AS.
  Remove duplicate listing of Cris arch from README
  kbuild: more doc. cleanups
  doc: make doc. for maxcpus= more visible
  drivers/net/eexpress.c: remove duplicate comment
  add a help text for BLK_DEV_GENERIC
  correct a dead URL in the IP_MULTICAST help text
  fix the BAYCOM_SER_HDX help text
  fix SCSI_SCAN_ASYNC help text
  trivial documentation patch for platform.txt
  Fix typos concerning hierarchy
  Fix comment typo "spin_lock_irqrestore".
  Fix misspellings of "agressive".
  drivers/scsi/a100u2w.c: trivial typo patch
  Correct trivial typo in log2.h.
  Remove useless FIND_FIRST_BIT() macro from cardbus.c.
  ...
2007-02-19 13:29:02 -08:00
Russell King
8213084125 Merge NetSilicon NS93xx tree
Fixed conflicts:

	arch/arm/Makefile
	arch/arm/mm/Kconfig

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-18 11:27:07 +00:00
Russell King
f69eda00d4 Merge AT91, EP93xx, General devel, PXA, S3C, V6+ and Xscale trees 2007-02-17 20:09:53 +00:00
Uwe Kleine-König
9918cda523 [ARM] 4210/1: base for new machine type "NetSilicon NS9360"
Signed-off-by: Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-17 20:05:45 +00:00
Robert P. J. Day
6340aa61b1 kbuild: Replace remaining "depends" with "depends on"
Replace the very few remaining "depends" Kconfig directives with
"depends on".

Signed-off-by: Robert P. J. Day <rpjday@mindspring.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
2007-02-17 19:05:24 +01:00
Catalin Marinas
382266ad5a [ARM] 4135/1: Add support for the L210/L220 cache controllers
This patch adds the support for the L210/L220 (outer) cache
controller. The cache range operations are done by index/way since L2
cache controller only accepts physical addresses.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-11 16:48:02 +00:00
Andrew Victor
b2c6561605 [ARM] 4145/2: AT91: Add support for AT91SAM9263 processor
Add support for the Atmel AT91SAM9263 processor.  It is similar to the
AT91SAM9260 but with more integrated peripherals, 5 GPIO banks, etc.

Original patch from Nicolas Ferre.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-08 14:55:24 +00:00
Catalin Marinas
953233dc99 [ARM] 4134/1: Add generic support for outer caches
The outer cache can be L2 as on RealView/EB MPCore platform or even L3
or further on ARMv7 cores. This patch adds the generic support for
flushing the outer cache in the DMA operations.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-08 14:49:40 +00:00
Linus Torvalds
ea14fad0d4 Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (76 commits)
  [ARM] 4002/1: S3C24XX: leave parent IRQs unmasked
  [ARM] 4001/1: S3C24XX: shorten reboot time
  [ARM] 3983/2: remove unused argument to __bug()
  [ARM] 4000/1: Osiris: add third serial port in
  [ARM] 3999/1: RX3715: suspend to RAM support
  [ARM] 3998/1: VR1000: LED platform devices
  [ARM] 3995/1: iop13xx: add iop13xx support
  [ARM] 3968/1: iop13xx: add iop13xx_defconfig
  [ARM] Update mach-types
  [ARM] Allow gcc to optimise arm_add_memory a little more
  [ARM] 3991/1: i.MX/MX1 high resolution time source
  [ARM] 3990/1: i.MX/MX1 more precise PLL decode
  [ARM] 3986/1: H1940: suspend to RAM support
  [ARM] 3985/1: ixp4xx clocksource cleanup
  [ARM] 3984/1: ixp4xx/nslu2: Fix disk LED numbering (take 2)
  [ARM] 3994/1: ixp23xx: fix handling of pci master aborts
  [ARM] 3981/1: sched_clock for PXA2xx
  [ARM] 3980/1: extend the ARM Versatile sched_clock implementation from 32 to 63 bit
  [ARM] 3979/1: extend the SA11x0 sched_clock implementation from 32 to 63 bit period
  [ARM] 3978/1: macro to provide a 63-bit value from a 32-bit hardware counter
  ...
2006-12-07 15:40:39 -08:00
Russell King
6705cda24f [ARM] Merge individual ARM sub-trees
Merge:
 Atmel AT91RM9200 and AT91SAM9260 changes
 General ARM developments
 Disconfiguous memory cleanups
 64-bit/32-bit division and sched_clock extension patches
 EP93xx support changes
 IOP support changes

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-07 23:07:26 +00:00
Dan Williams
285f5fa7e9 [ARM] 3995/1: iop13xx: add iop13xx support
The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a
Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory
controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz
PCI-X interface, a x8 PCI-Express interface, and other peripherals to form
a system-on-a-chip RAID subsystem engine.

The iop342 processor replaces the SAS controller with a second Xscale core
for dual core embedded applications.

The iop341 processor is the single core version of iop342.

This patch supports the two Intel customer reference platforms iq81340mc
for external storage and iq81340sc for direct attach (HBA) development.

The developer's manual is available here:
ftp://download.intel.com/design/iio/docs/31503701.pdf

Changelog:
* removed virtual addresses from resource definitions
* cleaned up some unnecessary #include's

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-07 17:20:21 +00:00
Dan Williams
f5236225a3 [ARM] 3967/1: xsc3: make branch predication configurable on xsc3
Remove BTB_ENABLE from proc-xsc3.S

On some early revisions of xsc3 enabling the branch target buffer can cause
crashes, see erratum #42.

Cc: Lennert Buytenhek <buytenh@wantstofly.org>

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-01 23:40:37 +00:00
Matt LaPlante
3cb2fccc5f Fix misc Kconfig typos
Fix various Kconfig typos.

Signed-off-by: Matt LaPlante <kernel1@cyberdogtech.com>
Acked-by: Randy Dunlap <randy.dunlap@oracle.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-11-30 05:22:59 +01:00
Hyok S. Choi
6afd6fae1d [ARM] nommu: confirms the CR_V bit in nommu mode
In nommu mode, the exception vector location depends on the platforms.
Some of the implementations may have some special exception control
forwarding method in their ROM/flash and for some of them has its own
re-mapping mechanism by the h/w.

This patch introduces a special configuration CONFIG_CPU_HIGH_VECTOR which
turns on the CR_V bit in nommu mode. The CR_V bit is turned off by default.
This feature depends on CP15 and does not supported by ARM740.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-28 20:17:30 +01:00
Hyok S. Choi
0f45d7f36b [ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores.
There is no FSR/FAR register on no-CP15 or MPU cores. This patch adds a
dummy abort handler which returns zero for the base restored Data Abort
model !CPU_CP15_MMU cores. The abort-lv4t.S is still used with the fix-up
for the base updated Data Abort model cores.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-28 20:15:46 +01:00
Russell King
6b237a355a [ARM] Make !MMU CPUs depend on !MMU
Don't offer non-MMU based CPUs for selection when CONFIG_MMU is
set.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:44:39 +01:00
Hyok S. Choi
f37f46eb1c [ARM] nommu: add ARM946E-S core support
This patch adds ARM946E-S core support which has typically 8KB I&D cache.
It has a MPU and supports ARMv5TE instruction set.

Because the ARM946E-S core can be synthesizable with various cache size,
CONFIG_CPU_DCACHE_SIZE is defined for vendor specific configurations.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:39:19 +01:00
Hyok S. Choi
d60674eb5d [ARM] nommu: add ARM940T core support
This patch adds ARM940T core support which has 4KB D-cache, 4KB I-cache
and a MPU.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:39:18 +01:00
Hyok S. Choi
43f5f0146e [ARM] nommu: add ARM9TDMI core support
This patch adds ARM9TDMI core support which has no cache and no CP15
register(no memory control unit).

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:39:17 +01:00
Hyok S. Choi
b731c3118d [ARM] nommu: add ARM740T core support
This patch adds ARM740T core support which has a MPU and 4KB or 8KB cache.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:39:17 +01:00
Hyok S. Choi
07e0da78ab [ARM] nommu: add ARM7TDMI core support
This patch adds ARM7TDMI core support which has no cache and no CP15
register(no memory control unit).

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:39:17 +01:00
Hyok S. Choi
f12d0d7c77 [ARM] nommu: manage the CP15 things
All the current CP15 access codes in ARM arch can be categorized and
conditioned by the defines as follows:

     Related operation	Safe condition
  a. any CP15 access	!CPU_CP15
  b. alignment trap	CPU_CP15_MMU
  c. D-cache(C-bit)	CPU_CP15
  d. I-cache		CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
				CPU_ARM720 || CPU_ARM740 ||
				CPU_XSCALE || CPU_XSC3 )
  e. alternate vector	CPU_CP15 && !CPU_ARM740
  f. TTB		CPU_CP15_MMU
  g. Domain		CPU_CP15_MMU
  h. FSR/FAR		CPU_CP15_MMU

For example, alternate vector is supported if and only if
"CPU_CP15 && !CPU_ARM740" is satisfied.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:34:30 +01:00
Hyok S. Choi
fefdaa06cc [ARM] nommu: defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU
By merging of uClinux/ARM, we need to treat various CPU cores which have
MMU, MPU or even none for memory management. The memory management
coprocessors are controlled by CP15 register set and the ARM core family
can be categorized by 5 groups by the register ;
  G-a. CP15 is MMU : 610, 710, 720, 920, 922, 925, 926, 1020, 1020e, 1022,
		v6 and the derivations sa1100, sa110, xscale, xsc3.
  G-b. CP15 is MPU : 740, 940, 946, 996, 1156.
  G-c. CP15 is MPU or MMU : 1026 (selectable by schematic design)
  G-d. CP15 is exist, but nothing for memory managemnt : 966, 968.
  G-e. no-CP15 : 7tdmi, 9tdmi, 9e, 9ej

This patch defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU. Thus the
family can be defined as :
  - CPU_CP15 only : G-d
  - CPU_CP15_MMU(implies CPU_CP15) : G-a, G-c(selectable)
  - CPU_CP15_MPU(implies CPU_CP15) : G-b, G-c(selectable)
  - !CPU_CP15 : G-e

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:28:47 +01:00
Lennert Buytenhek
3f7e5815f4 [ARM] 3817/1: iop3xx: split the iop3xx mach into iop32x and iop33x
Split the iop3xx mach type into iop32x and iop33x -- split the config
symbols, and move the code in the mach-iop3xx directory to the mach-iop32x
and mach-iop33x directories.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-25 10:25:36 +01:00
Lennert Buytenhek
260e98edc8 [ARM] 3761/1: fix armv4t breakage after adding thumb interworking to userspace helpers
Patch from Lennert Buytenhek

On armv4t systems, we have always compiled the kernel with -march=armv4
instead of -march=armv4t, which means that any use of bx will bomb out.

Commit ba9b5d7637 introduced the use of
bx in the kernel, which means we need to compile with -march=armv4t on
armv4t systems now.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-08-28 12:51:20 +01:00
Andrew Victor
8fc5ffa063 [ARM] 3675/2: Preparing for AT91SAM926 support
Patch from Andrew Victor

This prepares the way for adding support for the new Atmel AT91SAM926x
processors.

Major changes:
- Rename time.c to at91rm9200_time.c
- Rename common.c to at91rm9200.c
- Introduce ARCH_AT91, of which ARCH_AT91RM9200, ARCH_AT91SAM9260 and
ARCH_AT91SAM9261 are dependent.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-29 16:06:33 +01:00
Hyok S. Choi
f9c21a6ee7 [ARM] nommu: avoid selecting TLB and CPU specific copy code
Since uclinux doesn't make use of the TLB, including the TLB
maintainence and CPU-optimised copypage functions does not
make sense.  Remove them.

(This is part of one of Hyok's patches.)

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:47 +01:00
Russell King
60b6cf6851 [ARM] nommu: we need the TLS register emulation for nommu mode
Since there can be no fixed location for the TLS value with nommu
systems, we must provide TLS register emulation in order to support
TLS binaries on CPUs without the thread register.

Part of a patch from Hyok S. Choi, and cleaned up by rmk.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:43 +01:00
Ben Dooks
3434d9d9fc [ARM] 3636/1: S3C2412: Add selection of CPU_ARM926
Patch from Ben Dooks

Select CONFIG_CPU_ARM926 when CONFIG_CPU_S3C2412 is
selected.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-24 21:21:28 +01:00
Sascha Hauer
bb6d8c8828 [ARM] 3567/2: arm: base support for Hilscher netX
Patch from Sascha Hauer

This patch adds the base support for Hilscher's netX network
processors.

Signed-off-by: Robert Schwebel <r.schwebel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-19 15:27:53 +01:00
Vitaly Wool
78818e477b [ARM] 3466/1: [2/3] Support for Philips PNX4008 platform: chip support
Patch from Vitaly Wool

This patch adds basic chip support for PNX4008 ARM platform.
It's basically the same as the previous one, but with the rmk's
comments taken into account.

Signed-off-by: Vitaly Wool <vwool@ru.mvista.com>
Signed-off-by: Dmitry Pervushin <dpervushin@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-18 16:16:55 +01:00
Lennert Buytenhek
23bdf86aa0 [ARM] 3377/2: add support for intel xsc3 core
Patch from Lennert Buytenhek

This patch adds support for the new XScale v3 core.  This is an
ARMv5 ISA core with the following additions:

- L2 cache
- I/O coherency support (on select chipsets)
- Low-Locality Reference cache attributes (replaces mini-cache)
- Supersections (v6 compatible)
- 36-bit addressing (v6 compatible)
- Single instruction cache line clean/invalidate
- LRU cache replacement (vs round-robin)

I attempted to merge the XSC3 support into proc-xscale.S, but XSC3
cores have separate errata and have to handle things like L2, so it
is simpler to keep it separate.

L2 cache support is currently a build option because the L2 enable
bit must be set before we enable the MMU and there is no easy way to
capture command line parameters at this point.

There are still optimizations that can be done such as using LLR for
copypage (in theory using the exisiting mini-cache code) but those
can be addressed down the road.

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-28 21:00:40 +01:00
Russell King
0003cedfc5 Merge nommu tree
Fix merge conflict in arch/arm/mm/proc-xscale.S

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-25 22:08:55 +00:00
Lennert Buytenhek
e7736d47a1 [ARM] 3369/1: ep93xx: add core cirrus ep93xx support
Patch from Lennert Buytenhek

This patch adds support for the Cirrus ep93xx series of CPUs.  The
ep93xx is an ARM920T based CPU with two VICs, PL010 based UARTs,
IrDA, MaverickCrunch floating point coprocessor, between 24 and 64
GPIOs, ethernet, OHCI USB and, depending on the model, pcmcia, raster
engine, graphics accelerator, IDE controller and a bunch of other
stuff.

This patch adds the core ep93xx support code, and support for the
Glomation GESBC-9312-sx and the Technologic Systems TS-72xx SBCs.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-21 22:06:11 +00:00
Russell King
48fa14f761 [ARM] select TLS_REG_EMUL and NEEDS_SYSCALL_FOR_CMPXCHG
Rather than having a growing dependency line, use select to set
these configuration symbols.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-21 22:03:26 +00:00
SAN People
73a59c1c4a [ARM] 3240/2: AT91RM9200 support for 2.6 (Core)
Patch from SAN People

Following changes were made to clock.c:

1) Replaced <asm/hardware/clock.h> with <linux/clk.h>
2) Removed old unused clk_enable & clk_disable.
3) Replaced clk_use/clk_unuse with clk_enable/clk_disable.

Otherwise it's the same as the previous patch.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-09 17:05:41 +00:00
Russell King
0fec53a24a [ARM] Remove EPXA10DB machine support
EPXA10DB seems to be uncared for:
- the "PLD" code has never been merged
- no one has reported that this platform has been broken since
  at least 2.6.10
- interest seems to have dried up around March 2003.

Therefore, remove EPXA10DB support.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-08 22:37:46 +00:00
Tony Lindgren
1dbae815a7 [ARM] 3145/1: OMAP 3a/5: Add support for omap24xx
Patch from Tony Lindgren

This patch adds support for omap24xx series of processors.
The files live in arch/arm/mach-omap2, and share common
files with omap15xx and omap16xx processors in
arch/arm/plat-omap.

Omap24xx support was originally added for 2.6.9 by TI.
This code was then improved and integrated to share common
code with omap15xx and omap16xx processors by various
omap developers, such as Paul Mundt, Juha Yrjola, Imre Deak,
Tony Lindgren, Richard Woodruff, Nishant Menon, Komal Shah
et al.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-10 14:26:51 +00:00
Tony Lindgren
3179a01939 [ARM] 3141/1: OMAP 1/5: Update omap1 specific files
Patch from Tony Lindgren

This patch syncs the mainline kernel with linux-omap tree.
The highlights of the patch are:

- Omap1 serial pport and framebuffer init updates by Imre Deak

- Add support for omap310 processor and Palm Tungsten E PDA
  by Laurent Gonzales, Romain Goyet, et al. Omap310 and
  omap1510 processors are now handled as omap15xx.

- Omap1 specific changes to shared omap clock framework
  by Tony Lindgren

- Omap1 specific changes to shared omap pin mux framework
  by Tony Lindgren

- Other misc fixes, such as update memory timings for smc91x,
  omap1 specific device initialization etc.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-10 14:26:48 +00:00
Russell King
4a5f79e7e6 [ARM SMP] Add configuration option for ARMv6K processors
The 'K' extension adds several new instructions to the ARMv6 ISA
which are primerily useful for SMP.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-03 15:48:21 +00:00
Catalin Marinas
8ad68bbf7a [ARM] Add support for ARM RealView board
Support for RealView EB.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-31 14:25:02 +00:00
Catalin Marinas
e03eb5272b [ARM] 2954/1: Allow D and I cache and branch prediction disabling for ARMv6
Patch from Catalin Marinas

There is no reason to not allow these config options. They are useful when
the hardware has problems.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-05 23:06:36 +01:00
Sean Lee
22d8be866e [ARM] 2852/1: Correct the mistake in arch/arm/mm/Kconfig file
Patch from Sean Lee

In the arch/arm/mm/Kconfig file, the CPU_DCACHE_WRITETHROUGH
option is depend on the CPU_DISABLE_DCACHE, but the "Disable
D-Cache" option is configured as CPU_DCACHE_DISABLE.
The CPU_DISABLE_DCACHE should be CPU_DCACHE_DISABLE

Signed-off-by: Sean Lee <beginner2arm@eyou.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-17 09:28:26 +01:00
Tony Lindgren
b288f75ffa [PATCH] ARM: 2798/1: OMAP update 2/11: Change ARM Kconfig to support omap1 and omap2
Patch from Tony Lindgren

This patch by Paul Mundt and other OMAP developers modifies
ARM specific Kconfig to allow sharing code between OMAP1 and
OMAP2 architectures.
In order to share code between OMAP1 and OMAP2, all OMAP1
specific code is moved into mach-omap1 directory in the
following patch. A new mach-omap2 directory will be added
later on.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-07-10 19:58:08 +01:00
Bellido Nicolas
038c5b6025 [PATCH] ARM: 2686/2: AAEC-2000 Core support
Patch from Bellido Nicolas

Core support for AAEC-2000 based platforms.
This is an updated version of the previous patch, and takes
into account Russell's comments.
AAED-2000 default configuration will follow as soon
as some problems with the bootloader are sorted out...

Signed-off-by: Nicolas Bellido
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-20 18:51:05 +01:00
Nicolas Pitre
dcef1f6346 [PATCH] ARM: 2664/2: add support for atomic ops on pre-ARMv6 SMP systems
Patch from Nicolas Pitre

Not that there might be many of them on the planet, but at least RMK
apparently has one.

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-08 19:00:47 +01:00
Russell King
f8f98a9335 [PATCH] ARM: Fix Xscale copy_page implementation
The ARM copypage changes in 2.6.12-rc4-git1 removed the preempt locking
from the copypage functions which broke the XScale implementation.
This patch fixes the locking on XScale and removes the now unneeded
minicache code.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
Checked-by: Richard Purdie
2005-06-08 15:28:24 +01:00
Nicolas Pitre
70489c88d0 [PATCH] ARM: 2680/1: refine TLS reg availability some more again
Patch from Nicolas Pitre

Not all ARMv6 processors implement the TLS register.

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-05-12 19:27:12 +01:00
Nicolas Pitre
fa4354359f [PATCH] ARM: 2663/2: I can't type
Patch from Nicolas Pitre

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-05-10 17:36:29 +01:00
Nicolas Pitre
4b0e07a556 [PATCH] ARM: 2663/1: straightify TLS register emulation a bit more
Patch from Nicolas Pitre

This better express things, and should cover RMK's weird SMP toys.

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-05-05 23:24:45 +01:00
Nicolas Pitre
48af721540 [PATCH] ARM: 2662/1: missing "default y" for CONFIG_HAS_TLS_REG
Patch from Nicolas Pitre

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-05-03 22:57:56 +01:00
Nicolas Pitre
2d2669b629 [PATCH] ARM: 2651/3: kernel helpers for NPTL support
Patch from Nicolas Pitre

This patch entirely reworks the kernel assistance for NPTL on ARM.
In particular this provides an efficient way to retrieve the TLS
value and perform atomic operations without any instruction emulation
nor special system call.  This even allows for pre ARMv6 binaries to
be forward compatible with SMP systems without any penalty.
The problematic and performance critical operations are performed
through segment of kernel provided user code reachable from user space
at a fixed address in kernel memory.  Those fixed entry points are
within the vector page so we basically get it for free as no extra
memory page is required and nothing else may be mapped at that
location anyway.
This is different from (but doesn't preclude) a full blown VDSO
implementation, however a VDSO would prevent some assembly tricks with
constants that allows for efficient branching to those code segments.
And since those code segments only use a few cycles before returning to
user code, the overhead of a VDSO far call would add a significant
overhead to such minimalistic operations.
The ARM_NR_set_tls syscall also changed number.  This is done for two
reasons:
1) this patch changes the way the TLS value was previously meant to be
   retrieved, therefore we ensure whatever library using the old way
   gets fixed (they only exist in private tree at the moment since the
   NPTL work is still progressing).
2) the previous number was allocated in a range causing an undefined
   instruction trap on kernels not supporting that syscall and it was
   determined that allocating it in a range returning -ENOSYS would be
   much nicer for libraries trying to determine if the feature is
   present or not.

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29 22:08:33 +01:00
Linus Torvalds
1da177e4c3 Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!
2005-04-16 15:20:36 -07:00