Add node for the NXP LPC18xx EEPROM memory which can be found in
NXP LPC185x/3x and LPC435x/3x/2x/1x devices.
Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Most of the peripherals on LPC18xx/43xx devices have their reset
lines hooked up to internal reset controller (RGU). Add reset
entries to the device nodes so a driver can use the reset line.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
NXP LPC SoCs family, which includes LPC18xx/LPC43xx, provides a State
Configurable Timer (SCT) which can be configured as a Pulse Width
Modulator.
Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Add node for the watchdog timer found on LPC18xx/LPC43xx.
Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Add dmas entries to the four UART peripherals on LPC18xx/43xx devices
so that DMA can be used to transfer data.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Add dmas entries to the two SSP peripherals on LPC18xx/43xx devices
so that DMA can be used to transfer data.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Add node for the DMA multiplexer placed in front of the PL080 DMA
controller on lpc18xx/43xx devices.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Add the NXP LPC1773 SPIFI (SPI Flash Interface) flash controller
node to the dtsi for all lpc18xx/43xx devices.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Add the NXP LPC1850 RGU (Reset Generation Unit) reset controller
node to the dtsi for all lpc18xx/43xx devices.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
All devices in the LPC18xx/43xx familiy contain a ARM PL172
MultiPort Memory Controller (MPMC).
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
NXP LPC185x and LPC435x/70 devices contain a ARM PL111 lcd controller.
Signed-off-by: Joachim Eastwood <joachim.eastwood@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add the USB OTG phy under the CREG syscon node and attach it to
the USB0 EHCI controller.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
The CREG block contains a collection of miscellaneous
configuration register like Ethernet phy mode, low
power clocks and DMA multiplexer. These registers
needs to be accessed from other drivers and syscon
provides this capability.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Add gpio and mapping between pinctrl/gpio namespace with
gpio-ranges property.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Add CGU and CCU clock-controller nodes for lpc18xx together with
the fixed input clocks. Also remove the temporary fixed-factor
pll1 clock from both lpc18xx and lpc4350-hitex-eval DTS now that
proper clock drivers are inplace.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
NXP LPC18xx/43xx SoCs are very similar devices and should be able to
share a common base (lpc18xx.dtsi). Diffences between the devices are
put in a dtsi which is specific to that device.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
