Commit Graph

23 Commits

Author SHA1 Message Date
Stefan Agner
60ad8467c1 ARM: imx: pllv3: add shift for frequency multiplier
Add shift capabilties for the frequency multiplier (DIV_SELECT) to
support Vybrid's USB PLL oddity. The PLL3 and PLL7 are the only
PLL control registers which have the DIV_SELECT bit shifted by
one. Be aware, there are known documentation errors in the
reference manual too.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-05 20:53:05 +08:00
Lucas Stach
e0fed5133c ARM: imx: add CPU clock type
This implements a virtual clock used to abstract away
all the steps needed in order to change the ARM clock,
so we don't have to push all this clock handling into
the cpufreq driver.

While it will be used for i.MX53 at first it is generic
enough to be used on i.MX6 later on.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23 14:56:19 +08:00
Shawn Guo
19d863446a ARM: imx: add an exclusive gate clock type
There are a couple of gate clocks are mutually exclusive on i.MX6, i.e.
LVDSCLK1_IBEN and LVDSCLK1_OBEN.  They cannot be enabled simultaneously.
This patches adds an exclusive gate clock type specifically for such
case.  The clock driver will need to call imx_clk_gate_exclusive() to
register a gate clock with parameter exclusive_mask indicating the mask
of gate bits which are mutually exclusive to this gate clock.

Right now, it only handles the exclusive gate clocks which are defined
in a single hardware register, which is the case we're running into
today.  But it can be extended to handle exclusive gate clocks defined
in different registers later if needed.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16 10:06:48 +08:00
Alexander Shiyan
6525169028 ARM: i.MX21 clk: Clock initialization rework
This patch perform rework i.MX21 clock initialization. This includes
adding missing clocks and sort clocks by register address.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-18 16:11:31 +08:00
Alexander Shiyan
229be9c141 ARM: i.MX clk: Move clock check function in common location
This patch moves clock check function in common i.MX location
and switch i.MX clk drivers to use this new function.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-18 16:10:12 +08:00
Shawn Guo
f9f28cdf21 ARM: imx: add shared gate clock support
It's quite common on i.MX that one gate bit controls the gating of
multiple clocks, i.e. this is a shared gate.  The patch adds the
function imx_clk_gate2_shared() for such case.  The clocks controlled
by the same gate bits should call this function with a pointer to a
single share count variable, so that the gate bits will only be
operated on the first enabling and the last disabling of these shared
gate clocks.

Thanks to Gerhard Sittig <gsi@denx.de> for this idea.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-12 22:58:48 +08:00
Linus Torvalds
bef4a0ab98 The common clk framework changes for 3.12 are dominated by clock driver
patches, both new drivers and fixes to existing. A high percentage of
 these are for Samsung platforms like Exynos. Core framework fixes and
 some new features like automagical clock re-parenting round out the
 patches.
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Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux

Pull clock framework changes from Michael Turquette:
 "The common clk framework changes for 3.12 are dominated by clock
  driver patches, both new drivers and fixes to existing.  A high
  percentage of these are for Samsung platforms like Exynos.  Core
  framework fixes and some new features like automagical clock
  re-parenting round out the patches"

* tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits)
  clk: only call get_parent if there is one
  clk: samsung: exynos5250: Simplify registration of PLL rate tables
  clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
  clk: samsung: exynos4: Register PLL rate tables for Exynos4210
  clk: samsung: exynos4: Reorder registration of mout_vpllsrc
  clk: samsung: pll: Add support for rate configuration of PLL46xx
  clk: samsung: pll: Use new registration method for PLL46xx
  clk: samsung: pll: Add support for rate configuration of PLL45xx
  clk: samsung: pll: Use new registration method for PLL45xx
  clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
  clk: samsung: exynos4: Remove checks for DT node
  clk: samsung: exynos4: Remove unused static clkdev aliases
  clk: samsung: Modify _get_rate() helper to use __clk_lookup()
  clk: samsung: exynos4: Use separate aliases for cpufreq related clocks
  clocksource: samsung_pwm_timer: Get clock from device tree
  ARM: dts: exynos4: Specify PWM clocks in PWM node
  pwm: samsung: Update DT bindings documentation to cover clocks
  clk: Move symbol export to proper location
  clk: fix new_parent dereference before null check
  clk: wm831x: Initialise wm831x pointer on init
  ...
2013-09-09 15:49:04 -07:00
James Hogan
819c1de344 clk: add CLK_SET_RATE_NO_REPARENT flag
Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes
being reparented during clk_set_rate.

To avoid breaking existing platforms, all callers of clk_register_mux()
are adjusted to pass the new flag. Platform maintainers are encouraged
to remove the flag if they wish to allow mux reparenting on set_rate.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Andrew Chew <achew@nvidia.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: spear-devel@list.st.com
Cc: linux-tegra@vger.kernel.org
Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Stephen Warren <swarren@nvidia.com> [tegra]
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi]
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-19 12:27:17 -07:00
Liu Ying
dfd871442e ARM: imx6: change some clocks to fixup clocks
All the clocks controlled by the register 'CCM Serial Clock
Multiplexer Register 1' should be fixup clocks. This patch
changes those clocks from basic multiplexer or divider clocks
to fixup clocks.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16 13:11:25 +08:00
Liu Ying
a49e6c4b82 ARM: imx: add common clock support for fixup mux
One register may have several fields to control some clocks. It
is possible that the read/write values of some fields may map to
different real functional values, so writing to the other fields
in the same register may break a working clock tree. A real case
is the aclk_podf field in the register 'CCM Serial Clock Multiplexer
Register 1' of i.MX6Q/SDL SoC. This patch introduces a fixup hook
for multiplexer clock which is called before writing a value to
clock registers to support this kind of multiplexer clocks.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16 13:11:24 +08:00
Liu Ying
cbe7fc8aae ARM: imx: add common clock support for fixup div
One register may have several fields to control some clocks. It
is possible that the read/write values of some fields may map to
different real functional values, so writing to the other fields
in the same register may break a working clock tree. A real case
is the aclk_podf field in the register 'CCM Serial Clock Multiplexer
Register 1' of i.MX6Q/SDL SoC. This patch introduces a fixup hook
for divider clock which is called before writing a value to clock
registers to support this kind of divider clocks.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16 13:11:24 +08:00
Jiada Wang
71ed547743 ARM: imx: remove MLB PLL from pllv3
MLB PLL should be handled internally in MLB driver,
so remove it from pllv3.

Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17 15:45:12 +08:00
Martin Fuzzey
75f83d06c3 ARM: i.MX5: Allow DT clock providers
Currently clock providers defined in the DT are not registered
on i.MX5 platforms since of_clk_init() is not called.

This is not a problem for the SOC's own clocks, which are registered
in code,  but prevents the DT being used to define clocks for external
hardware.

Fix this by calling of_clk_init() and actually using the DT to obtain
the 4 SOC fixed clocks.
These are already defined in the DT but were previously just used to
manually obtain the rate.

Fall back to the old scheme for non DT platforms.

Since the same method may be useful for other i.MX platforms
implement the imx_obtain_fixed_clock() function in common code.

Actually changing other i.MX platforms to use this should be done
later by someone with access to the appropriate hardware.

Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17 15:45:09 +08:00
Philipp Zabel
3ce921702b ARM i.MX: Add imx_clk_divider_flags and imx_clk_mux_flags
The default is for dividers to set CLK_SET_PARENT_RATE and for muxes to
not set that flag. In the LDB clock tree, we need the opposite, so add
functions to create divider and mux clocks with configurable flags.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12 19:01:44 +08:00
Sascha Hauer
2b254693be ARM i.MX6: remove gate_mask from pllv3
Now that the additional enable bits in the enet PLL are handled
as gates, the gate_mask is identical for all plls. Remove the
gate_mask from the code and use the BM_PLL_ENABLE bit for
enabling/disabling the PLL.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
2012-11-22 15:32:39 +01:00
Sascha Hauer
3a84d17bb3 ARM: i.MX remove last leftovers from legacy clock support
This also removes mach/clock.h along the way

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
2012-09-12 11:46:51 +02:00
Shawn Guo
32af7a830f ARM: imx: add common clock support for clk busy
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-05-02 12:08:26 +02:00
Shawn Guo
a10bd67f19 ARM: imx: add common clock support for pfd
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-05-02 12:08:20 +02:00
Sascha Hauer
b75c015143 ARM i.MX: Add common clock support for 2bit gate
This gate consists of two bits:

0b00: clk disabled
0b01: clk enabled in run mode and disabled in sleep mode
0b11: clk enabled

Currently only disabled and enabled are supported. As it's unlikely
that we find something like this in another SoC create a i.MX specific
clk helper for this.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-05-02 12:08:13 +02:00
Shawn Guo
a3f6b9dbf2 ARM: imx: add common clock support for pllv3
This PLL is found on i.MX6 SoCs

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-05-02 12:08:06 +02:00
Sascha Hauer
a547b816a8 ARM i.MX: Add common clock support for pllv2
This PLL is found on i.MX51 and i.MX53

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-05-02 12:07:59 +02:00
Sascha Hauer
2af9e6db14 ARM i.MX: Add common clock support for pllv1
The pllv1 is found on i.MX1, i.M25, i.MX27, i.MX31 and i.MX35.
Currently only reading the rate is supported.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-05-02 12:07:53 +02:00
Sascha Hauer
6c7b06850c ARM i.MX: prepare for common clock framework
- Add necessary #ifdefs for CONFIG_COMMON_CLOCK
- Add a global spinlock to protect the CCM registers

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-04-25 17:03:46 +02:00