Commit Graph

32 Commits

Author SHA1 Message Date
John Garry
f1dc358408 scsi: hisi_sas: keep CHL_INT2 masked for v2 HW
None of the CHL_INT2 interrupts are serviced in the channel irq ISR, so
leave the interrupt source masked.  The interrupt mask is initially set
in init_reg_v2_hw().

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-09-14 12:54:17 -04:00
John Garry
4fde02ad66 scsi: hisi_sas: save delivery queue write pointer
Optimise by saving an avoidable read in the get_free_slot function.  The
delivery queue write pointer will only be updated by software, so don't
bother re-reading what was already written in the previous call to
start_delivery function.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-09-14 12:54:17 -04:00
John Garry
e6c346f303 scsi: hisi_sas: save completion queue read pointer
Optimise by saving an avoidable read in the cq interrupt.  The queue
read pointer will only be updated by software, so don't bother
re-reading what was already written in the previous interrupt.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-09-14 12:54:17 -04:00
John Garry
df032d0e4d scsi: hisi_sas: add v2 hw slot complete internal abort support
Add code in slot_complete_v2_hw() to deal with the slots which have
completed due to internal abort.

The status codes have the following meaning:

- STAT_IO_ABORTED: the IO has been aborted due to internal abort,
  whether by device or individual abort command

- STAT_IO_COMPLETE: internal abort command has completed successfully
  for device or individual abort command

- STAT_IO_NO_DEVICE: internal abort command has completed for device but
  cannot find any IO

- STAT_IO_NOT_VALID: internal abort command has completed for single
  command but could not find the command

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-08-25 22:38:54 -04:00
John Garry
a3e665d91f scsi: hisi_sas: add prep_abort_v2_hw()
Add function to prepare the an internal abort for v2 hw.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-08-25 22:38:54 -04:00
John Garry
308d85d176 hisi_sas: fix the inconsistent lock issue reported by CONFIG_PROVE_LOCKING
It is not necessary to surround call to
notify_port_event(, PORTE_BROADCAST_RCVD) by spin_lock_irqsave(),
so remove.
This was causing a warn, as below:

    =================================
    [ INFO: inconsistent lock state ]
    4.4.8+ #12 Not tainted
    ---------------------------------
    inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage.
    kworker/u64:1/168 [HC0[0]:SC0[0]:HE1:SE1] takes:
     (&(&hisi_hba->lock)->rlock){?.....}, at: [<ffffffc00052c708>] alloc_dev_quirk_v2_hw+0x48/0xec
    {IN-HARDIRQ-W} state was registered at:
      [<ffffffc0000fc764>] mark_lock+0x19c/0x6a0
      [<ffffffc0000fdc14>] __lock_acquire+0xa2c/0x1d00
      [<ffffffc0000ff654>] lock_acquire+0x58/0x7c
      [<ffffffc0008b609c>] _raw_spin_lock_irqsave+0x54/0x6c
      [<ffffffc00052d3c0>] int_chnl_int_v2_hw+0x1c4/0x248
      [<ffffffc0001098e8>] handle_irq_event_percpu+0x9c/0x144
      [<ffffffc0001099d4>] handle_irq_event+0x44/0x74
      [<ffffffc00010cd68>] handle_fasteoi_irq+0xb4/0x188
      [<ffffffc000108ea8>] generic_handle_irq+0x24/0x38
      [<ffffffc0001091fc>] __handle_domain_irq+0x60/0xac
      [<ffffffc00008261c>] gic_handle_irq+0xcc/0x168
      [<ffffffc0000855ac>] el1_irq+0x6c/0xe0
      [<ffffffc0000f7414>] default_idle_call+0x1c/0x34
      [<ffffffc0000f7654>] cpu_startup_entry+0x1d4/0x228
      [<ffffffc0008aecd8>] rest_init+0x150/0x160
      [<ffffffc000c4b95c>] start_kernel+0x3a4/0x3b8
      [<00000000008bb000>] 0x8bb000
    irq event stamp: 32661
    hardirqs last  enabled at (32661): [<ffffffc0008b41a8>] __mutex_unlock_slowpath+0x108/0x18c
    hardirqs last disabled at (32660): [<ffffffc0008b40e4>] __mutex_unlock_slowpath+0x44/0x18c
    softirqs last  enabled at (25114): [<ffffffc0000bde68>] __do_softirq+0x210/0x27c
    softirqs last disabled at (25095): [<ffffffc0000be224>] irq_exit+0x9c/0xe8

    other info that might help us debug this:
     Possible unsafe locking scenario:

           CPU0
           ----
      lock(&(&hisi_hba->lock)->rlock);
      <Interrupt>
        lock(&(&hisi_hba->lock)->rlock);

     *** DEADLOCK ***

    2 locks held by kworker/u64:1/168:
     #0:  ("%s"shost->work_q_name){++++.+}, at: [<ffffffc0000d2980>] process_one_work+0x134/0x3cc
     #1:  ((&sw->work)#2){+.+.+.}, at: [<ffffffc0000d2980>] process_one_work+0x134/0x3cc

    stack backtrace:
    CPU: 4 PID: 168 Comm: kworker/u64:1 Not tainted 4.4.8+ #12
    Hardware name: Huawei Technologies Co., Ltd. D03/D03, BIOS 1.12 01/01/1900
    Workqueue: scsi_wq_1 sas_discover_domain
    Call trace:
    [<ffffffc000089988>] dump_backtrace+0x0/0x114
    [<ffffffc000089ab0>] show_stack+0x14/0x1c
    [<ffffffc00035ac50>] dump_stack+0xb4/0xf0
    [<ffffffc0000fc524>] print_usage_bug+0x210/0x2b4
    [<ffffffc0000fcbc4>] mark_lock+0x5fc/0x6a0
    [<ffffffc0000fd9e8>] __lock_acquire+0x800/0x1d00
    [<ffffffc0000ff654>] lock_acquire+0x58/0x7c
    [<ffffffc0008b5edc>] _raw_spin_lock+0x44/0x58
    [<ffffffc00052c708>] alloc_dev_quirk_v2_hw+0x48/0xec
    [<ffffffc000528214>] hisi_sas_dev_found+0x48/0x1b8
    [<ffffffc00051a9b8>] sas_notify_lldd_dev_found+0x34/0xe0
    [<ffffffc00051e5e8>] sas_discover_root_expander+0x58/0x128
    [<ffffffc00051b38c>] sas_discover_domain+0x4bc/0x564
    [<ffffffc0000d29ec>] process_one_work+0x1a0/0x3cc
    [<ffffffc0000d2d50>] worker_thread+0x138/0x438
    [<ffffffc0000d9494>] kthread+0xdc/0xf0
    [<ffffffc000085c50>] ret_from_fork+0x10/0x40

Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-07-12 23:16:31 -04:00
John Garry
50408712b5 hisi_sas: add v2 hw ACPI support
Add support in v2 hw driver for ACPI.

A check on whether an ACPI handle is available for the device is used to
decide on whether to use ACPI reset handler or syscon for hw reset.

Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-07-12 23:16:31 -04:00
Hannes Reinecke
661ce1f0c4 libata/libsas: Define ATA_CMD_NCQ_NON_DATA
Define the NCQ NON DATA command and update libsas to handle it
correctly.

Signed-off-by: Hannes Reinecke <hare@suse.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2016-05-09 12:36:44 -04:00
Hannes Reinecke
ef026b18bb libsas: enable FPDMA SEND/RECEIVE
Update libsas and dependent drivers to handle FPDMA
SEND/RECEIVE correctly.

Signed-off-by: Hannes Reinecke <hare@suse.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2016-05-09 12:36:44 -04:00
John Garry
b2bdaf2bde hisi_sas: add alloc_dev_quirk_v2_hw()
Add custom version of function to allocate device,
alloc_dev_quirk_v2_hw().  For sata devices the device id bit0 should be
0.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinicke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-04-15 16:53:23 -04:00
John Garry
330fa7f314 hisi_sas: add slot_index_alloc_quirk_v2_hw()
Add v2 hw custom function slot_index_alloc_quirk_v2_hw().  SAS devices
should have IPTT bit0 equal to 1.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinicke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-04-15 16:53:23 -04:00
John Garry
f76a0b4940 hisi_sas: for v2 hw only set ITCT qw2 for SAS device
This patch fixes the ITCT table setup as it should be configured
differently for SAS and SATA devices.  For SATA disks there is no need
to set qw2 (already zeroed).  Also, link parameters for Bus inactive
limit, max connection time limit, and reject to open limit timers
parameters are changed to match global config register,
MAX_CON_TIME_LIMIT_TIME, as recommended by hw team.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-04-15 16:53:17 -04:00
John Garry
11826e5dc7 hisi_sas: add v2 hw support for >4 SATA phys
This patch adds support for directly attaching SATA disks to phy
4-8. The problem was that only registers concerned with phy 0-3 were
being considered in sata_int_v2_hw().  The issue was not detected
previously as the development board only exposed phy 0-3; the new board
provides access to 8 phys.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-04-15 16:53:16 -04:00
John Garry
3a429d5ab6 hisi_sas: fix v2 hw multiple SATA disk issue
Intermittently it is found that when multiple SATA disks are directly
connected to the host that some disks are not detected.  The problem is
that all set bitfields in ENT_INT_SRC1 are cleared for all phys in
sata_int_v2_hw() - it should clear the set bit for the phy being
serviced.

Also unnecessary double-write to ENT_INT_SRC1 and ENT_INT_SRC_MSK1 is
removed (remaining writes are done at end label).

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-04-15 16:53:16 -04:00
John Garry
7524926826 hisi_sas: use device linkrate in MCR for v2 hw
Contrary to the field name, the MCR (max connection rate) in the ITCT
should hold the device linkrate (linkrate of the connected phy), and not
the max linkrate.

This fixes an issue seen where some SATA drives connected through an
expander which would not attach.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-04-15 16:53:15 -04:00
John Garry
9c8ee657cf hisi_sas: use slot abort in v2 hw
When TRANS_TX_ERR_FRAME_TXED error occurs in
a slot, the command should be re-attempted.
This error is equivalent to meaning that the queue
is full in the sdev (and not the host).
A superflous debug statement is also removed in the
slot complete handler.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-29 21:00:03 -05:00
John Garry
63fb11b878 hisi_sas: add v2 tmf functions
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-23 21:27:02 -05:00
John Garry
e8fed0e9a9 hisi_sas: add v2 slot error handler
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-23 21:27:02 -05:00
John Garry
6f2ff1a131 hisi_sas: add v2 path to send ATA command
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-23 21:27:02 -05:00
John Garry
85b2c3c040 hisi_sas: add v2 code for itct setup and free
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-23 21:27:02 -05:00
John Garry
c2d8939275 hisi_sas: add v2 code to send smp command
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-23 21:27:02 -05:00
John Garry
8c36e31d6e hisi_sas: add v2 path to send ssp frame
Include code to prep ssp frame and deliver to hardware.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-23 21:27:02 -05:00
John Garry
31a9cfa6f7 hisi_sas: add v2 cq interrupt handler
Also include slot_complete_v2_hw handler

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-23 21:27:02 -05:00
John Garry
d43f9cdb7f hisi_sas: add v2 SATA interrupt handler
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-23 21:27:02 -05:00
John Garry
d3bf3d84d3 hisi_sas: add v2 channel interrupt handler
This also includes broadcast handler. Unlike v1 hw, broadcast does not
have its own dedicated interrupt.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-23 21:27:02 -05:00
John Garry
5473c06081 hisi_sas: add v2 phy down handler
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-23 21:27:02 -05:00
John Garry
7911e66f1f hisi_sas: add v2 int init and phy up handler
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-23 21:27:02 -05:00
John Garry
29a2042863 hisi_sas: add v2 phy init code
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-23 21:27:02 -05:00
John Garry
806bb768a2 hisi_sas: add init_id_frame_v2_hw()
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-23 21:27:02 -05:00
John Garry
94eac9e1ab hisi_sas: add v2 hw init
Add code to initialise the hardware.

Support is also added to deal with the "am-max-transmissions" (amt)
limitation in hip06 controller #1. This is how many connection requests
we can send on the system bus before waiting for a response.  Due to
chip bus design, controller #1 is limited to 32 amt, while, by design, a
controller supports 64.  The default value for the nibbles in the
relevant registers is 0x40; these need to be programmed with 0x20.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-23 21:27:02 -05:00
John Garry
45c901b848 hisi_sas: add v2 register definitions
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-23 21:27:02 -05:00
John Garry
3417ba8abd hisi_sas: add bare v2 hw driver
Just add enough to build and init the module.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-23 21:27:02 -05:00