Pull ARM SoC driver updates from Arnd Bergmann:
"A number of new drivers get added this time, along with many
low-priority bugfixes. The most interesting changes by subsystem are:
bus drivers:
- Updates to the Broadcom bus interface driver to support newer SoC
types
- The TI OMAP sysc driver now supports updated DT bindings
memory controllers:
- A new driver for Tegra186 gets added
- A new driver for the ti-emif sram, to allow relocating
suspend/resume handlers there
SoC specific:
- A new driver for Qualcomm QMI, the interface to the modem on MSM
SoCs
- A new driver for power domains on the actions S700 SoC
- A driver for the Xilinx Zynq VCU logicoreIP
reset controllers:
- A new driver for Amlogic Meson-AGX
- various bug fixes
tee subsystem:
- A new user interface got added to enable asynchronous communication
with the TEE supplicant.
- A new method of using user space memory for communication with the
TEE is added"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (84 commits)
of: platform: fix OF node refcount leak
soc: fsl: guts: Add a NULL check for devm_kasprintf()
bus: ti-sysc: Fix smartreflex sysc mask
psci: add CPU_IDLE dependency
soc: xilinx: Fix Kconfig alignment
soc: xilinx: xlnx_vcu: Use bitwise & rather than logical && on clkoutdiv
soc: xilinx: xlnx_vcu: Depends on HAS_IOMEM for xlnx_vcu
soc: bcm: brcmstb: Be multi-platform compatible
soc: brcmstb: biuctrl: exit without warning on non brcmstb platforms
Revert "soc: brcmstb: Only register SoC device on STB platforms"
bus: omap: add MODULE_LICENSE tags
soc: brcmstb: Only register SoC device on STB platforms
tee: shm: Potential NULL dereference calling tee_shm_register()
soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver
dt-bindings: soc: xilinx: Add DT bindings to xlnx_vcu driver
soc: xilinx: Create folder structure for soc specific drivers
of: platform: populate /firmware/ node from of_platform_default_populate_init()
soc: samsung: Add SPDX license identifiers
soc: qcom: smp2p: Use common error handling code in qcom_smp2p_probe()
tee: shm: don't put_page on null shm->pages
...
Pull "arm: Xilinx ZynqMP SoC fixes for v4.16" from Michal Simek:
- Fix Kconfig dependency
- Fix vcu clkoutdiv calculation
* tag 'zynqmp-soc-fixes-for-4.16' of https://github.com/Xilinx/linux-xlnx:
soc: xilinx: Fix Kconfig alignment
soc: xilinx: xlnx_vcu: Use bitwise & rather than logical && on clkoutdiv
soc: xilinx: xlnx_vcu: Depends on HAS_IOMEM for xlnx_vcu
Pull "FSL/NXP SoC drivers updates for 4.16" from Li Yang:
This adds new SoC support and more error path handling to the guts
driver.
* tag 'soc-fsl-for-4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/leo/linux:
soc: fsl: guts: Add a NULL check for devm_kasprintf()
soc: fsl: support GUTS driver for ls1012a/ls1046a
devm_kasprintf() may fail, so we should better add a NULL check
and propagate an error on failure.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Currently clkoutdiv is being operated on by a logical && operator rather
than a bitwise & operator. This looks incorrect as these should be bit
flag operations.
Addresses-Coverity-ID: 1463959 ("Logical vs. bitwise operator")
Fixes: cee8113a29 ("soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver")
Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
Acked-by: Dhaval Shah <dshah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
xlnx_vcu driver uses devm_ioremap_nocache, which is included
only when HAS_IOMEM is enabled.
drivers/soc/xilinx/xlnx_vcu.o: In function `xvcu_probe':
xlnx_vcu.c:(.text+0x116): undefined reference to `devm_ioremap_nocache'
xlnx_vcu.c:(.text+0x1ae): undefined reference to `devm_ioremap_nocache'
Signed-off-by: Dhaval Shah <dshah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
We were making a bunch of wrong assumptions that turned out to blow out
on non-Broadcom STB platforms:
- we would return -ENODEV from brcmstb_soc_device_early_init() if we
could not find the sun_top_ctrl device node, this is not an error
in the context of a multi-platform kernel
- we would still try to register the Broadcom STB SoC device, even if we
are not running on such a platform
While at it, also fix the sun_top_ctrl device_node leaks while we change
the flow of brcmstb_soc_device_init() and
brcmstb_soc_device_early_init().
Fixes: f780429adf ("soc: brcmstb: biuctrl: Move to early_initcall")
Signed-off-by: Thierry Reding <treding@nvidia.com>
[florian: Combine all of Thierry's patch in one go for easier review]
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Currently if this driver is included, we get the following warning
on any platforms irrespective of whether it's brcmstb platform or not.
"
brcmstb: biuctrl: missing BIU control node
brcmstb: biuctrl: MCP: Unable to disable write pairing!
"
This patch allows to exit early without any warning messages on non
brcmstb platforms as it's meaningless for them.
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Gregory Fong <gregory.0xf0@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Fixes: f780429adf ("soc: brcmstb: biuctrl: Move to early_initcall")
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
[florian: Add fixes tag, make initcall non fatal]
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This reverts commit 23a0d84799.
Patch has issues that's being addressed by the Florian and he will
follow up with a new patch to address the original issue.
Signed-off-by: Olof Johansson <olof@lixom.net>
After moving the SoC device initialization to an early initcall in
commit f780429adf ("soc: brcmstb: biuctrl: Move to early_initcall"),
the Broadcom STB SoC device is registered on all platforms if support
for the device is enabled in the kernel configuration.
This causes an additional SoC device to appear on platforms that already
register a native one. In case of Tegra the STB SoC device is registered
as soc0 (with totally meaningless content in the sysfs attributes) and
causes various scripts and programs to fail because they don't know how
to parse that data.
To fix this, duplicate the check from brcmstb_soc_device_early_init()
that already prevents the code from doing anything nonsensical on non-
STB platforms.
Fixes: f780429adf ("soc: brcmstb: biuctrl: Move to early_initcall")
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Xilinx ZYNQMP logicoreIP Init driver is based on the new
LogiCoreIP design created. This driver provides the processing system
and programmable logic isolation. Set the frequency based on the clock
information get from the logicoreIP register set.
Signed-off-by: Dhaval Shah <dshah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Pull "i.MX drivers update for 4.16" from Shawn Guo:
- Update i.MX GPC driver to support PCI power domain of i.MX6SX SoC.
* tag 'imx-drivers-4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx: gpc: Add i.MX6SX PCI power domain
Second Round of Renesas ARM Based SoC Updates for v4.16
* rcar-sysc: Keep wakeup sources active during system suspend
Geert Uytterhoeven says "If an R-Car SYSC slave device is part of the
CPG/MSTP or CPG/MSSR Clock Domain and to be used as a wakeup source, it
must be kept active during system suspend.
Currently this is handled in device-specific drivers by explicitly
increasing the use count of the module clock when the device is
configured as a wakeup source. However, the proper way to prevent the
device from being stopped is to inform this requirement to the genpd
core, by setting the GENPD_FLAG_ACTIVE_WAKEUP flag.
Note that this will only affect devices configured as wakeup sources."
* tag 'renesas-soc2-for-v4.16' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
soc: renesas: rcar-sysc: Keep wakeup sources active during system suspend
Signed-off-by: Olof Johansson <olof@lixom.net>
Actions Semi SoC drivers for v4.16
The SPS power domain driver is extended for S700 SoC.
* tag 'actions-drivers-for-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions:
soc: actions: sps: Add S700
Signed-off-by: Olof Johansson <olof@lixom.net>
This pull request contains Broadcom ARM/ARM64 based SoCs drivers changes for
4.16, please pull the following:
- Arnd provides an update to the Raspberry Pi firmware interface and uses time64_t to
print the time to make it more future proof
- Florian provides a set of updates to make the Broadcom STB Bus Interface Unit code
work on newer ARM64-based chips, as well as perform the correct interface tuning
for these chips to reach the expected performance
* tag 'arm-soc/for-4.16/drivers' of http://github.com/Broadcom/stblinux:
soc: brcmstb: biuctrl: Move to early_initcall
soc: brcmstb: Split initialization
soc: brcmstb: biuctrl: Fine tune B53 MCP interface settings
soc: brcmstb: biuctrl: Wire-up new registers
soc: brcmstb: biuctrl: Prepare for saving/restoring other registers
soc: brcmstb: Correct CPU_CREDIT_REG offset for Brahma-B53 CPUs
soc: brcmstb: Make CPU credit offset more parameterized
dt-bindings: arm: brcmstb: Correct BIUCTRL node documentation
dt-bindings: arm: Add entry for Broadcom Brahma-B53
firmware: raspberrypi: print time using time64_t
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds an SoC driver for the Gemini. Currently there
is only one thing not fitting into any other framework,
and that is the bus arbitration setting.
All Gemini vendor trees seem to be setting this register to
exactly the same arbitration so we just add a small code
snippet to do this at subsys_init() time before any other
drivers kick in.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Add a jump target so that a specific error message is stored only once
at the end of this function implementation.
* Replace two calls of the function "dev_err" by goto statements.
* Adjust two condition checks.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Pull "arm: Updates for soc driver for v4.15-next" from Matthias Brugger:
- change kconfig entry for armv7 SoCs to be more generic
- add support for mt2701 scpsys driver
binding documentation
extend driver to allow the bus protection to overwrite the register
* tag 'v4.15-next-soc' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
soc: mediatek: add MT2712 scpsys support
soc: mediatek: add dependent clock jpgdec/audio for scpsys
soc: mediatek: extend bus protection API
dt-bindings: soc: add MT2712 power dt-bindings
ARM: mediatek: use more generic prompts for SoCs with ARMv7
Pull "soc/tegra: Changes for v4.16-rc1" from Thierry Reding:
Fuse and chip ID support for Tegra186 is added in this set of changes,
followed by some unification work for the PMC driver in order to avoid
code duplication between Tegra186 and prior chips.
This also contains a couple of fixes for reading fuses on Tegra20.
* tag 'tegra-for-4.16-soc-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: fuse: Explicitly request DMA channel from APB DMA driver
soc/tegra: fuse: Fix reading registers using DMA on Tegra20
soc/tegra: pmc: Consolidate Tegra186 support
soc/tegra: pmc: Parameterize driver
soc/tegra: fuse: Add Tegra186 chip ID support
soc/tegra: fuse: Warn if accessing unmapped registers
soc/tegra: fuse: Move register mapping check
soc/tegra: fuse: Add Tegra186 support
dt-bindings: misc: Add Tegra186 MISC registers bindings
Currently fuse driver requests DMA channel from an arbitrary DMA device,
it is not a problem since there is only one DMA provider for Tegra20 yet,
but it may become troublesome if another provider will appear.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
FUSE driver doesn't configure DMA channel properly, because of it DMA
transfer is never issued and tegra20_fuse_read() always return 0x0.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Pull "Renesas ARM Based SoC Updates for v4.16" from Simon Horman:
* Identify R-Car M3-W ES1.1
Geert Uytterhoeven says "The Product Register of R-Car M3-W ES1.1
incorrectly identifies the SoC revision as ES2.0. Add a workaround to
fix this."
It is my understanding that this is likely to be forwards-compatibile.
* tag 'renesas-soc-for-v4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
soc: renesas: Identify R-Car M3-W ES1.1
There are dependent clock jpgdec/audio in scpsys on MT2712,
and will exist three dependent clocks on MT2712 VDEC.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
MT2712 add "set/clear" bus control register to each control register set
instead of providing only one "enable" control register, we could avoid
the read-modify-write racing by declaring "bus_prot_reg_update" as "false"
in scp_soc_data or declaring as "true" to use the legacy update method.
By improving the mtk-infracfg bus protection implementation to
support set/clear bus protection control method by IC configuration.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Being called during early_initcall() is early enough that it occurs
before SMP initialization, which is all we care about for the Bus
Interface Unit configuration.
This solves lack of BIU initialization on ARM64 platforms where we do
not have an anchor where to put the BIU initialization (since there are
no machine descriptors).
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
We may need access to family_id and product_id fairly early on boot for
other parts of the code (e.g: biuctrl.c), so split the initialization
between an early_init() and an arch_initcall() which allows us to do
that.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
In order to achieve expected MCP bus throughput on 3 particular chips:
7268, 7271 and 7278, do the appropriate programming of the MCP
interface: increase number of MCP write credits, turn on write-back
throttling when present.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add definitions for B53 systems register: CPU_MCP_FLOW_REG and
CPU_WRITEBACK_CTRL_REG. These register will be saved and restored
accordingly.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
In preparation for saving/restoring additional registers required on
some newer platforms (7268, 7271, 7278), migrate the code to use enums
and helper functions to access registers.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
On Broadcom Brahma-B53 CPUs, the CPU_CREDIT_REG offset got moved to
0x0b0 instead of 0x184, correct this such that we correcty
enable/disable write-pairing for these chips.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
In preparation for fixing and changing values in the CPU_CREDIT_REG
register for B53-based systems, make the offset parameterized.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Drivers that needs to communicate with a remote QMI service all has to
perform the operations of discovering the service, encoding and decoding
the messages and operate the socket. This introduces an abstraction for
these common operations, reducing most of the duplication in such cases.
Acked-by: Chris Lew <clew@codeaurora.org>
Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the helper library for encoding and decoding QMI encoded messages.
The implementation is taken from lib/qmi_encdec.c of the Qualcomm kernel
(msm-3.18).
Modifications has been made to the public API, source buffers has been
made const and the debug-logging part was omitted, for now.
Acked-by: Chris Lew <clew@codeaurora.org>
Tested-by: Chris Lew <clew@codeaurora.org>
Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Attempt to acquire the APCS IPC through the mailbox framework and fall
back to the old syscon based approach, to allow us to move away from
using the syscon.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This change resolves a new compile-time warning
when built as a loadable module:
WARNING: modpost: missing MODULE_LICENSE() in drivers/soc/qcom/rmtfs_mem.o
see include/linux/module.h for more information
This adds the license as "GPL v2", which matches the header of the file.
MODULE_DESCRIPTION and MODULE_AUTHOR are also added.
Signed-off-by: Jesse Chan <jc@linux.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Fix child-node lookup during probe, which ended up searching the whole
device tree depth-first starting at the parent rather than just matching
on its children.
Note that the original premature free of the parent node has already
been fixed separately.
Also note that this pattern of looking up the first child node with a
given property is rare enough that a generic helper is probably not
warranted.
Fixes: c97c4090ff ("soc: qcom: smsm: Add driver for Qualcomm SMSM")
Fixes: 3e8b554114 ("soc: qcom: smsm: fix of_node refcnting problem")
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Clark <robdclark@gmail.com>
Signed-off-by: Johan Hovold <johan@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
If an R-Car SYSC slave device is part of the CPG/MSTP or CPG/MSSR Clock
Domain and to be used as a wakeup source, it must be kept active during
system suspend.
Currently this is handled in device-specific drivers by explicitly
increasing the use count of the module clock when the device is
configured as a wakeup source. However, the proper way to prevent the
device from being stopped is to inform this requirement to the genpd
core, by setting the GENPD_FLAG_ACTIVE_WAKEUP flag.
Note that this will only affect devices configured as wakeup sources.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
If source string longer than max, kstrndup will alloc max+1 space.
So, we should make sure the result will not over limit.
Signed-off-by: Ma Shimiao <mashimiao.fnst@cn.fujitsu.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
Move Tegra186 support to the consolidated PMC driver to reduce some of
the duplication and also gain I/O pad functionality on the new SoC as a
side-effect.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Parameterize some aspects of the driver in preparation for Tegra186 PMC
support. Initially the Tegra186 driver had been split off into an extra
driver, but it turns out the backwards-compatibility break isn't as bad
as originally assumed, so with a little parameterization the same code
can be used to keep supporting all SoC generations.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The register region containing chip ID information has been relocated in
Tegra186 and changed in backwards-incompatible ways. Add a compatible
string to allow the driver to make the distinction.
Signed-off-by: Thierry Reding <treding@nvidia.com>
