Commit Graph

982974 Commits

Author SHA1 Message Date
Tero Kristo
0a000aeb8b soc: ti: omap-prm: omap5: add genpd support for remaining PRM instances
Add genpd support for mpu, dsp, coreaon, core, iva, cam, dss, gpu,
l3init, custefuse, wkupaon and emu instances.

Cc: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-19 15:09:01 +02:00
Tony Lindgren
11fdf598d0 ARM: OMAP2+: Drop legacy platform data for dra7 gpmc
We can now probe devices with ti-sysc interconnect driver and dts
data. Let's drop the related platform data and custom ti,hwmods
dts property.

Cc: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-19 15:09:01 +02:00
Tony Lindgren
ae57d15589 ARM: dts: Configure interconnect target module for dra7 iva
We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver.

Cc: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-19 15:09:01 +02:00
Tero Kristo
1021b37ecd ARM: dts: dra7: add remaining PRM instances
Add remaining PRM instances for the dra7 SoC. Additionally enable the
genpd support for them.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-19 15:09:00 +02:00
Tero Kristo
5a68c87afd soc: ti: omap-prm: dra7: add genpd support for remaining PRM instances
Add genpd support for mpu, dsp, ipu, coreaon, core, iva, cam, dss, gpu,
l3init, l4per, custefuse, wkupaon, emu, eve, rtc and vpe instances.

Cc: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-19 15:09:00 +02:00
Tony Lindgren
57f5720136 clk: ti: dra7: Drop idlest polling from IVA clkctrl clocks
Similar to what we've done for IPU and DSP let's ignore the status bit
for the IVA clkctrl register.

The clkctrl status won't change unless the related rstctrl is deasserted,
and the rstctrl status won't change unless the clkctrl is enabled.

Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Suman Anna <s-anna@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-19 15:09:00 +02:00
Rafael J. Wysocki
de15e20f50 Merge branch 'acpi-fan'
* acpi-fan:
  ACPI: fan: Initialize performance state sysfs attribute
2020-11-19 14:03:52 +01:00
Rafael J. Wysocki
3a8ac4d396 Merge branch 'pm-cpuidle'
* pm-cpuidle:
  cpuidle: tegra: Annotate tegra_pm_set_cpu_in_lp2() with RCU_NONIDLE
2020-11-19 14:02:18 +01:00
Ranjani Sridharan
a27b421f1d
ASoC: pcm: call snd_soc_dapm_stream_stop() in soc_pcm_hw_clean
Currently, the SND_SOC_DAPM_STREAM_START event is sent during
pcm_prepare() but the SND_SOC_DAPM_STREAM_STOP event is
sent only in dpcm_fe_dai_shutdown() after soc_pcm_close().
This results in an imbalance between when the DAPM widgets
receive the PRE/POST_PMU/PMD events. So call
snd_soc_dapm_stream_stop() in soc_pcm_hw_clean() before the
snd_soc_pcm_component_hw_free() to keep the stream_stop DAPM
event balanced with the stream_start event in soc_pm_prepare().

Also, in order to prevent duplicate DAPM stream events,
remove the call for DAPM STREAM_START event in dpcm_fe_dai_prepare()
and the call for DAPM STREAM_STOP event in dpcm_fe_dai_shutdown().

Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20201117215001.163107-1-ranjani.sridharan@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19 13:00:05 +00:00
Kai Vehmanen
caebea04b9
ASoC: SOF: Intel: add hw specific PCM constraints
Part of PCM constraints are set based on DSP topology, but rest
should be set based on hardware capabilities. Add PCM constraints
for Intel platforms:

- Add constraint for the period count to be integer. This avoids
  wrap-arounds of the DMA circular buffer in middle of a period.

- Align period size to dword/32bit as per HDA spec.

Both constraints are aligned with current implementation in snd-hda-intel
driver.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20201118140545.2138895-2-kai.vehmanen@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19 13:00:04 +00:00
Kai Vehmanen
9983ac49b7
ASoC: SOF: relax PCM period and buffer size constraints
Current SOF implementation limits period and buffer sizes to multiples
of period_min. Period_min is defined in topology, but is in practise set
to align with the SOF DSP timer tick (typically 1ms).

While this approach helps user-space to avoid period sizes, which are
not aligned to the DSP timer tick, it causes problems to applications
which want to align data processing size to that of ALSA period size.
One example is JACK audio server, which limits period sizes to power of
two values.

Other ALSA drivers where audio data transfer is driven by a timer tick,
like USB, do not constraint period and buffer sizes to exact multiple of
the timer tick.

To align SOF to follow the same behaviour, drop the additional alignment
constraints. As a side-effect, this patch can cause irregularity to
period wakeup timing. This happens when application chooses settings
which were previously forbidden. For example, if application configures
period size to 2^14 bytes and audio config of S32_LE/2ch/48000Hz, one
period represents 42.667ms of audio. Without this patch, this
configuration is not allowed by SOF. With the patch applied,
configuration is allowed but the wakeups are paced by the DSP timer
tick, which is typically 1ms. Application will see period wakeups with a
42/43/42/43ms repeating pattern.

Both approaches are valid within ALSA context, but relaxing the
constraints is better aligned with existing applications and other ALSA
drivers like USB audio.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20201118140545.2138895-1-kai.vehmanen@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19 13:00:03 +00:00
Piotr Maziarz
73ea3a5dbb
ASoC: Intel: catpt: select WANT_DEV_COREDUMP
Select WANT_DEV_COREDUMP for catpt driver.

Signed-off-by: Piotr Maziarz <piotrx.maziarz@linux.intel.com>
Signed-off-by: Gustaw Lewandowski <gustaw.lewandowski@linux.intel.com>

--
Changes in v2:
 - change should be added to catpt only

Acked-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20201117145223.21222-1-gustaw.lewandowski@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19 13:00:02 +00:00
Shengjiu Wang
53233e40c1
ASoC: fsl_sai: Correct the clock source for mclk0
On VF610, mclk0 = bus_clk;
On i.MX6SX/6UL/6ULL/7D, mclk0 = mclk1;
On i.MX7ULP, mclk0 = bus_clk;
On i.MX8QM/8QXP, mclk0 = bus_clk;
On i.MX8MQ/8MN/8MM/8MP, mclk0 = bus_clk;

So add variable mclk0_is_mclk1 in fsl_sai_soc_data to
distinguish these platforms.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/1605768038-4582-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19 13:00:01 +00:00
Krzysztof Kozlowski
61349f0f27
ASoC: sunxi: do not select COMMON_CLK to fix builds
COMMON_CLK is a user-selectable option with its own dependencies.  The
most important dependency is !HAVE_LEGACY_CLK.  User-selectable drivers
should not select COMMON_CLK because they will create a dependency cycle
and build failures.  For example on MIPS a configuration with COMMON_CLK
(selected by SND_SUN8I_CODEC) and HAVE_LEGACY_CLK (selected by
SOC_RT305X) is possible:

  WARNING: unmet direct dependencies detected for COMMON_CLK
    Depends on [n]: !HAVE_LEGACY_CLK [=y]
    Selected by [y]:
    - SND_SUN8I_CODEC [=y] && SOUND [=y] && !UML && SND [=y] && SND_SOC [=y] &&
      (ARCH_SUNXI || COMPILE_TEST [=y]) && OF [=y] && (MACH_SUN8I || ARM64 && ARCH_SUNXI || COMPILE_TEST [=y])

    /usr/bin/mips-linux-gnu-ld: drivers/clk/clk.o: in function `clk_set_rate':
    (.text+0xaeb4): multiple definition of `clk_set_rate'; arch/mips/ralink/clk.o:(.text+0x88): first defined here

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20201118201420.4878-1-krzk@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19 13:00:01 +00:00
Pierre-Louis Bossart
cf7f4a5320
ASoC: Intel: bdw-rt5677: add missing pm_ops
For some reason this ops is missing in 2 out of the 3 broadwell
drivers. Add to make sure ASoC takes care of power management.

Tested-by: Cezary Rojewski <cezary.rojewski@intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@linux.intel.com>
Reviewed-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Link: https://lore.kernel.org/r/20201112223825.39765-3-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19 12:59:48 +00:00
Pierre-Louis Bossart
7998c168a9
ASoC: Intel: broadwell: add missing pm_ops
For some reason this ops is missing in 2 out of the 3 broadwell
drivers. Add to make sure ASoC takes care of power management.

Tested-by: Cezary Rojewski <cezary.rojewski@intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@linux.intel.com>
Reviewed-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Link: https://lore.kernel.org/r/20201112223825.39765-2-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19 12:59:47 +00:00
Srinivas Kandagatla
58aad93015
ASoC: codecs: lpass-va-macro: add dapm widgets and routes
Add dapm widgets and routes for this codec.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20201105113458.12360-7-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19 12:59:09 +00:00
Srinivas Kandagatla
908e6b1df2
ASoC: codecs: lpass-va-macro: Add support to VA Macro
Qualcomm LPASS (Low Power Audio SubSystem) has internal codec
VA macro block which is used for connecting with DMICs.

This patch adds support to the codec part of the VA Macro block

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20201105113458.12360-6-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19 12:59:08 +00:00
Srinivas Kandagatla
67d99b23c8
ASoC: qcom: dt-bindings: add bindings for lpass va macro codec
This binding is for LPASS has internal codec VA macro which is
for connecting with DMICs.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20201105113458.12360-5-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19 12:59:07 +00:00
Srinivas Kandagatla
2c4066e5d4
ASoC: codecs: lpass-wsa-macro: add dapm widgets and route
This patch adds dapm widgets and routes on this codec

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20201105113458.12360-4-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19 12:59:07 +00:00
Srinivas Kandagatla
809bcbcece
ASoC: codecs: lpass-wsa-macro: Add support to WSA Macro
Qualcomm LPASS (Low Power Audio SubSystem) has internal codec
WSA macro block which is used for connecting with WSA Smart
speakers over soundwire.

This patch adds support to the codec part of the WSA Macro block.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20201105113458.12360-3-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19 12:59:06 +00:00
Srinivas Kandagatla
ccbd847f15
ASoC: qcom: dt-bindings: add bindings for lpass wsa macro codec
This binding is for LPASS has internal codec WSA macro which is
for connecting with WSA Smart speakers.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20201105113458.12360-2-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19 12:59:05 +00:00
Hans de Goede
fbdae7d6d0
ASoC: Intel: bytcr_rt5640: Fix HP Pavilion x2 Detachable quirks
The HP Pavilion x2 Detachable line comes in many variants:

1. Bay Trail SoC + AXP288 PMIC, Micro-USB charging (10-k010nz, ...)
   DMI_SYS_VENDOR: "Hewlett-Packard"
   DMI_PRODUCT_NAME: "HP Pavilion x2 Detachable PC 10"
   DMI_BOARD_NAME: "8021"

2. Bay Trail SoC + AXP288 PMIC, Type-C charging (10-n000nd, 10-n010nl, ...)
   DMI_SYS_VENDOR: "Hewlett-Packard"
   DMI_PRODUCT_NAME: "HP Pavilion x2 Detachable"
   DMI_BOARD_NAME: "815D"

3. Cherry Trail SoC + AXP288 PMIC, Type-C charging (10-n101ng, ...)
   DMI_SYS_VENDOR: "HP"
   DMI_PRODUCT_NAME: "HP Pavilion x2 Detachable"
   DMI_BOARD_NAME: "813E"

4. Cherry Trail SoC + TI PMIC, Type-C charging (10-p002nd, 10-p018wm, ...)
   DMI_SYS_VENDOR: "HP"
   DMI_PRODUCT_NAME: "HP x2 Detachable 10-p0XX"
   DMI_BOARD_NAME: "827C"

5. Cherry Trail SoC + TI PMIC, Type-C charging (x2-210-g2, ...)
   DMI_SYS_VENDOR: "HP"
   DMI_PRODUCT_NAME: "HP x2 210 G2"
   DMI_BOARD_NAME: "82F4"

Variant 1 needs the exact same quirk as variant 2, so relax the DMI check
for the existing quirk a bit so that it matches both variant 1 and 2
(note the other variants will still not match).

Variant 2 already has an existing quirk (which now also matches variant 1)

Variant 3 uses a cx2072x codec, so is not applicable here.

Variant 4 almost works with the defaults, but it also needs a quirk to
fix jack-detection, add a new quirk for this.

Variant 5 does use a RT5640 codec (based on old dmesg output), but was
otherwise not tested, keep using the defaults for this variant.

Fixes: ec8e8418ff ("ASoC: Intel: bytcr_rt5640: Add quirks for various devices")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20201118121515.11441-1-hdegoede@redhat.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19 12:58:23 +00:00
Daniel Axtens
da631f7fd6 powerpc/64s: rename pnv|pseries_setup_rfi_flush to _setup_security_mitigations
pseries|pnv_setup_rfi_flush already does the count cache flush setup, and
we just added entry and uaccess flushes. So the name is not very accurate
any more. In both platforms we then also immediately setup the STF flush.

Rename them to _setup_security_mitigations and fold the STF flush in.

Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2020-11-19 23:47:25 +11:00
Daniel Axtens
0d239f3b03 selftests/powerpc: refactor entry and rfi_flush tests
For simplicity in backporting, the original entry_flush test contained
a lot of duplicated code from the rfi_flush test. De-duplicate that code.

Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2020-11-19 23:47:23 +11:00
Daniel Axtens
89a83a0c69 selftests/powerpc: entry flush test
Add a test modelled on the RFI flush test which counts the number
of L1D misses doing a simple syscall with the entry flush on and off.

For simplicity of backporting, this test duplicates a lot of code from
rfi_flush. We clean that up in the next patch.

Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2020-11-19 23:47:20 +11:00
Michael Ellerman
178d52c6e8 powerpc: Only include kup-radix.h for 64-bit Book3S
In kup.h we currently include kup-radix.h for all 64-bit builds, which
includes Book3S and Book3E. The latter doesn't make sense, Book3E
never uses the Radix MMU.

This has worked up until now, but almost by accident, and the recent
uaccess flush changes introduced a build breakage on Book3E because of
the bad structure of the code.

So disentangle things so that we only use kup-radix.h for Book3S. This
requires some more stubs in kup.h and fixing an include in
syscall_64.c.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2020-11-19 23:47:20 +11:00
Nicholas Piggin
9a32a7e78b powerpc/64s: flush L1D after user accesses
IBM Power9 processors can speculatively operate on data in the L1 cache
before it has been completely validated, via a way-prediction mechanism. It
is not possible for an attacker to determine the contents of impermissible
memory using this method, since these systems implement a combination of
hardware and software security measures to prevent scenarios where
protected data could be leaked.

However these measures don't address the scenario where an attacker induces
the operating system to speculatively execute instructions using data that
the attacker controls. This can be used for example to speculatively bypass
"kernel user access prevention" techniques, as discovered by Anthony
Steinhauser of Google's Safeside Project. This is not an attack by itself,
but there is a possibility it could be used in conjunction with
side-channels or other weaknesses in the privileged code to construct an
attack.

This issue can be mitigated by flushing the L1 cache between privilege
boundaries of concern. This patch flushes the L1 cache after user accesses.

This is part of the fix for CVE-2020-4788.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2020-11-19 23:47:18 +11:00
Nicholas Piggin
f79643787e powerpc/64s: flush L1D on kernel entry
IBM Power9 processors can speculatively operate on data in the L1 cache
before it has been completely validated, via a way-prediction mechanism. It
is not possible for an attacker to determine the contents of impermissible
memory using this method, since these systems implement a combination of
hardware and software security measures to prevent scenarios where
protected data could be leaked.

However these measures don't address the scenario where an attacker induces
the operating system to speculatively execute instructions using data that
the attacker controls. This can be used for example to speculatively bypass
"kernel user access prevention" techniques, as discovered by Anthony
Steinhauser of Google's Safeside Project. This is not an attack by itself,
but there is a possibility it could be used in conjunction with
side-channels or other weaknesses in the privileged code to construct an
attack.

This issue can be mitigated by flushing the L1 cache between privilege
boundaries of concern. This patch flushes the L1 cache on kernel entry.

This is part of the fix for CVE-2020-4788.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2020-11-19 23:47:15 +11:00
Russell Currey
fcb48454c2 selftests/powerpc: rfi_flush: disable entry flush if present
We are about to add an entry flush. The rfi (exit) flush test measures
the number of L1D flushes over a syscall with the RFI flush enabled and
disabled. But if the entry flush is also enabled, the effect of enabling
and disabling the RFI flush is masked.

If there is a debugfs entry for the entry flush, disable it during the RFI
flush and restore it later.

Reported-by: Spoorthy S <spoorts2@in.ibm.com>
Signed-off-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2020-11-19 23:47:12 +11:00
Qinglang Miao
368ffd9adc ipmi: msghandler: Suppress suspicious RCU usage warning
while running ipmi, ipmi_smi_watcher_register() caused
a suspicious RCU usage warning.

-----

=============================
WARNING: suspicious RCU usage
5.10.0-rc3+ #1 Not tainted
-----------------------------
drivers/char/ipmi/ipmi_msghandler.c:750 RCU-list traversed in non-reader section!!
other info that might help us debug this:
rcu_scheduler_active = 2, debug_locks = 1
2 locks held by syz-executor.0/4254:
stack backtrace:
CPU: 0 PID: 4254 Comm: syz-executor.0 Not tainted 5.10.0-rc3+ #1
Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.13.0-1ubuntu1 04/ 01/2014
Call Trace:
dump_stack+0x19d/0x200
ipmi_smi_watcher_register+0x2d3/0x340 [ipmi_msghandler]
acpi_ipmi_init+0xb1/0x1000 [acpi_ipmi]
do_one_initcall+0x149/0x7e0
do_init_module+0x1ef/0x700
load_module+0x3467/0x4140
__do_sys_finit_module+0x10d/0x1a0
do_syscall_64+0x34/0x80
entry_SYSCALL_64_after_hwframe+0x44/0xa9
RIP: 0033:0x468ded

-----

It is safe because smi_watchers_mutex is locked and srcu_read_lock
has been used, so simply pass lockdep_is_held() to the
list_for_each_entry_rcu() to suppress this warning.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
Message-Id: <20201119070839.381-1-miaoqinglang@huawei.com>
Signed-off-by: Corey Minyard <cminyard@mvista.com>
2020-11-19 06:36:28 -06:00
Joel Stanley
4da595ddc0 soc: aspeed: Enable drivers with ARCH_ASPEED
Default the drivers to on as most configurations will use them.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-11-19 23:01:36 +10:30
Dan Carpenter
0f0c9c7022 soc: aspeed: Fix a reference leak in aspeed_socinfo_init()
This needs to call of_node_put(np) before returning if of_iomap() fails.

Fixes: e0218dca57 ("soc: aspeed: Add soc info driver")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20201113100850.GA168908@mwanda
Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-11-19 23:01:15 +10:30
Tom Rix
959b981dc7 soc: aspeed: remove unneeded semicolon
A semicolon is not needed after a switch statement.

Signed-off-by: Tom Rix <trix@redhat.com>
Link: https://lore.kernel.org/r/20201101150622.2288203-1-trix@redhat.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-11-19 23:01:14 +10:30
Tiezhu Yang
91c7a7e065 MIPS: Loongson64: Fix wrong scache size when execute lscpu
As the user manual and code comment said, Loongson-3 has 4-scache banks,
while Loongson-2K has only 2 banks, so we should multiply the number of
scache banks, this multiply operation should be done by c->scache.sets
instead of scache_size, otherwise we will get the wrong scache size when
execute lscpu. For example, the scache size should be 8192K instead of
2048K on the Loongson 3A3000 and 3A4000 platform, we can see the related
info in the following boot message:

[loongson@linux ~]$ dmesg | grep "Unified secondary cache"
[    0.000000] Unified secondary cache 8192kB 16-way, linesize 64 bytes.
[    4.061909] Unified secondary cache 8192kB 16-way, linesize 64 bytes.
[    4.125629] Unified secondary cache 8192kB 16-way, linesize 64 bytes.
[    4.188379] Unified secondary cache 8192kB 16-way, linesize 64 bytes.

E.g. without this patch:

[loongson@linux ~]$ cat /sys/devices/system/cpu/cpu*/cache/index2/size
2048K
2048K
2048K
2048K
[loongson@linux ~]$ lscpu | grep "L2 cache"
L2 cache:              2048K

With this patch:

[loongson@linux ~]$ cat /sys/devices/system/cpu/cpu*/cache/index2/size
8192K
8192K
8192K
8192K
[loongson@linux ~]$ lscpu | grep "L2 cache"
L2 cache:              8192K

Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-19 13:29:37 +01:00
Tiezhu Yang
6ce91ba858 MIPS: Remove cpu_has_6k_cache and cpu_has_8k_cache in cpu_cache_init()
Since commit 02cf211968 ("Cleanup the mess in cpu_cache_init."),
cpu_has_6k_cache and cpu_has_8k_cache have no user, r6k_cache_init()
and r8k_cache_init() are not defined for over 15 years, just remove
them.

Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-19 13:28:58 +01:00
Thomas Bogendoerfer
0df162e137 MIPS: mm: Clean up setup of protection map
Protection map difference between RIXI and non RIXI cpus is _PAGE_NO_EXEC
and _PAGE_NO_READ usage. Both already take care of cpu_has_rixi while
setting up the page bits. So we just need one setup of protection map
and can drop the now unused (and broken for RIXI) PAGE_* defines.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-19 13:27:18 +01:00
Thomas Bogendoerfer
ed2adb7421 MIPS: mm: shorten lines by using macro
Introduce helper macro to make lines shorter.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-19 13:27:06 +01:00
Thomas Bogendoerfer
411406a8c7 MIPS: kvm: Use vm_get_page_prot to get protection bits
MIPS protection bits are setup during runtime so using defines like
PAGE_SHARED ignores this runtime changes. Using vm_get_page_prot
to get correct page protection fixes this.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-19 13:26:53 +01:00
Tony Lindgren
fb0bf6aa8d ARM: OMAP2+: Drop legacy platform data for omap4 gpmc
We can now probe devices with ti-sysc interconnect driver and dts
data. Let's drop the related platform data and custom ti,hwmods
dts property.

Cc: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-19 14:26:47 +02:00
Tony Lindgren
dfdaf8643e ARM: OMAP2+: Drop legacy platform data for omap4 iva
We can now probe devices with ti-sysc interconnect driver and dts
data. Let's drop the related platform data and custom ti,hwmods
dts property.

Cc: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-19 14:26:47 +02:00
Tony Lindgren
399882c199 ARM: dts: Configure power domain for omap4 dsp
This allows shutting down the dsp domain when not in use.

Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-19 14:26:47 +02:00
Tony Lindgren
0c7815f306 ARM: dts: Configure power domain for omap4 dss
This allows shutting down dss domain when the screen blanks.

Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-19 14:26:47 +02:00
Tero Kristo
6d4b65e31a ARM: dts: omap4: add remaining PRM instances
Add remaining PRM instances for the omap4 SoC. Additionally enable the
genpd support for them.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-19 14:26:47 +02:00
Tero Kristo
773f0d89ac soc: ti: omap-prm: omap4: add genpd support for remaining PRM instances
Add genpd support for mpu, tesla, always_on_core, core, ivahd, cam, dss,
gfx, l3init, l4per, cefuse, wkup and emu instances.

Cc: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-19 14:26:47 +02:00
Thomas Bogendoerfer
724d554a11 MIPS: vdso: Use vma page protection for remapping
MIPS protection bits are setup during runtime so using defines like
PAGE_READONLY ignores these runtime changes. To fix this we simply
use the page protection of the setup vma.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-19 13:26:38 +01:00
Tony Lindgren
3614fb09f9 clk: ti: omap4: Drop idlest polling from IVA clkctrl clocks
Similar to what we've done for IPU and DSP let's ignore the status bit
for the IVA clkctrl register.

The clkctrl status won't change unless the related rstctrl is deasserted,
and the rstctrl status won't change unless the clkctrl is enabled.

Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Suman Anna <s-anna@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-19 14:21:27 +02:00
Christian König
3e3e59ef0c drm/ttm: fix DMA32 handling in the global page pool
When we have mixed DMA32 and non DMA32 device in one system
it could otherwise happen that the DMA32 device gets pages
it can't work with.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Link: https://patchwork.freedesktop.org/patch/401317/
2020-11-19 13:09:29 +01:00
Takashi Iwai
551310e735 ALSA: hda/ca0132: Fix compile warning without PCI
CONFIG_PCI=n leads to a compile warning like:
  sound/pci/hda/patch_ca0132.c:8214:10: warning: no case matching constant switch condition '0'
due to the missed handling of QUIRK_NONE in ca0132_mmio_init().
Fix it.

Fixes: bf2aa9ccc8 ("ALSA: hda/ca0132 - Cleanup ca0132_mmio_init function.")
Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20201119120404.16833-1-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2020-11-19 13:04:43 +01:00
Joel Stanley
2ba56f464f ARM: dts: aspeed: ast2600evb: Add MAC0
MAC0 was not functional in the AST2600A0 SoC. This has been resolved
with the A1, so allow use of this port on EVBs with the A1 and
subsequent revisions.

A0 EVBs will still boot with this change, but the first Ethernet device
will not be functional.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-11-19 22:31:18 +10:30