Commit Graph

11 Commits

Author SHA1 Message Date
Dinh Nguyen
112cadfd43 ARM: socfpga: dts: enable ethernet for Arria10 devkit
Update the arria10 gmac nodes with all the necessary properties for ethernet
to function on the Arria10 devkit.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-10 15:45:12 -07:00
Kevin Hilman
da8d2b5d92 SoCFPGA updates for v4.2 part 3
- Add SCU node for Arria 10
 - Add enable-method for cpu nodes
 - Add SDRAM controller binding doc
 - Enable gpio-leds on SoCFPGA Socrates board
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVbmTMAAoJEBmUBAuBoyj0iUsP/11m4hJBD2PT11MeXZZy4uWy
 ZzBGobhAWCcMKE/c00W+UpDZ18fXDs9oK3obAFOyDCvJgXAq0RTVZ6Vj5sdFqMHM
 inEnbHVQdYMwd0/WqBVoyNAluQMpSa3yg9YtcBCIzZCxX3DRWk18QAQycHczbxzp
 qM1Z8bXPSPBi5CCX0w68oxnOh+vN6dcz/CTXqMPpU+3Oo1b1h4yZXvLTp4rAboSn
 dr0OnnlD4LlAH0FhJkbVmrU++jeOaUZu491tUSm6EijK+a0ATNwHOn00OMdZYvrb
 AXvUXcjWwezaPx6b+XOAwYS2WFCSTWRcxUo+lmLB2UpzeHNAZp+V6hAtigVEq8au
 03619HXcbWfW2c2d+wDQ01xHA3t30rpWaVMWyf+UGMVoCKgDXYaNh3h5bwYIoUia
 hSqYACO/f3PkGlJrndGRuRMPaJKNE2ihaoJbHtzIBI5rcRnZ2RtRkdg6j6HWBdr4
 Um8Hsi+CJDtXBo4OoVYl8jqCp2Qh7Zq1bKQ99HYFDinQtxYr+Q4G5PsBc/UHDwC0
 0PBJUyneWeJlemKoewR6RRtx0d9IkA02T1ijaaOVjtYp9pU7JDMdkMtHbSgqnnNd
 bFWU49HHDzF92sOEu0wRT5SOlFp3VO2hs/jGWWDlWXrA1iJujuHFofuTEfFrlwLJ
 n5aKtM8w1JJfzWQ06/zz
 =nAUL
 -----END PGP SIGNATURE-----

Merge tag 'socfpga_dts_for_v4.2_part_3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt

SoCFPGA updates for v4.2 part 3
- Add SCU node for Arria 10
- Add enable-method for cpu nodes
- Add SDRAM controller binding doc
- Enable gpio-leds on SoCFPGA Socrates board

* tag 'socfpga_dts_for_v4.2_part_3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: socfpga: socrates: add gpio-leds
  ARM: socfpga: socrates: enable gpio0/1
  ARM: socfpga: dts: add sdram controller dt binding doc
  ARM: socfpga: dts: add enable-method property for cpu nodes
  ARM: socfpga: dts: add the a9-scu node for arria10
2015-06-10 15:40:59 -07:00
Dinh Nguyen
ebbce1bbc4 ARM: socfpga: dts: add enable-method property for cpu nodes
Add the enable-method property for the cpu node on socfpga.dtsi and
socfpga_arria10.dtsi. This is for CPU_METHOD_OF_DECLARE to use to enable
the secondary core.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-06-02 14:18:15 -05:00
Dinh Nguyen
479f8df04c ARM: socfpga: dts: add the a9-scu node for arria10
Add a dts node for the A9 SCU on the Arria10 platform.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-06-02 14:18:06 -05:00
Dinh Nguyen
da29d824a6 ARM: socfpga: dts: add clocks to the Arria10 platform
Add all the clock nodes for the Arria10 platform. At the same time, update
the peripherals with their respective clocks property.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: Add the l4_sys_free_clk node
2015-05-11 13:26:02 -05:00
Vince Bridgers
c01e8cdb7b ARM: socfpga: dts: Add tx-fifo-depth and rx-fifo-depth properties
Add tx-fifo-depth and rx-fifo-depth devicetree properties for socfpga
stmmac. These devicetree properties will be used to configure certain
features of the stmmac on the socfpga.

Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11 13:15:00 -05:00
Vince Bridgers
be9863cac2 ARM: socfpga: dts: Add multicast bins and unicast filter entries
Add multicast-filter-bins and perfect-filter-entries configuration properties
to the socfpga devicetree for the Arria 10 socfpga.

Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11 13:14:59 -05:00
Dinh Nguyen
74568da48f ARM: socfpga: dts: enable UART1 for the debug uart
Arria10 devkit is using UART1 for the debug uart port. Remove
unused aliases.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: Add removal of unused aliases
2015-05-11 13:14:59 -05:00
Dinh Nguyen
1dfb7d2fd6 ARM: socfpga: dts: disable the sdmmc, and uart nodes in the base arria10
Add status = "disabled" in the base DTSI for Arria10.  The SDMMC and uart
nodes should be enabled in the appropriate board file.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11 13:14:59 -05:00
Dinh Nguyen
08d6638f1a ARM: socfpga: dts: add cpu1-start-addr for Arria 10
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11 13:14:58 -05:00
Dinh Nguyen
475dc86d08 arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC
The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10
SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there
are enough differences to warrant a new base dtsi.

The differences are:
* 3 EMAC controllers
* 5 I2C controllers
* 3 SPI controllers
* 1.5 GHZ dual A9s
* Support for DDR4

Besides the usual memory map and IRQ changes, the clock framework will be
different, so this patch just adds the fixed-clocks.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-11-20 23:08:42 -06:00