Commit Graph

31 Commits

Author SHA1 Message Date
Thierry Reding
363541e8ee drm/tegra: dc: Remove redundant spinlock
The spinlock is only used to serialize accesses to the DC_CMD_INT_MASK
register. However, this register is accesses either with interrupts
masked (in tegra_crtc_atomic_enable()) or protected by the vbl_lock and
vblank_time_lock spinlocks of the DRM device. Therefore, these accesses
don't need any extra serialization and the lock can be removed.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21 14:52:35 +01:00
Thierry Reding
511c7023cf drm/tegra: dc: Support more formats
Also, split up formats into per-SoC lists because not all generations
support all of them. Note that the list is now exhaustive for all RGB
formats, but not for YUV and indexed formats.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21 14:52:29 +01:00
Thierry Reding
c57997bce4 drm/tegra: sor: Add Tegra186 support
The SOR found on Tegra186 is very similar to the one found on Tegra210
and earlier. However, due to some changes in the display architecture,
some programming sequences have changed and some register have moved
around.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13 14:36:36 +01:00
Thierry Reding
7772fdaef9 drm/tegra: Support ARGB and ABGR formats
These formats can easily be supported on all generations of Tegra.

Note that the XRGB and XBGR formats that we supported were in fact using
the ARGB and ABGR Tegra formats. This happened to work in cases where no
alpha was being considered. This change is also a fix for those formats.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13 14:16:39 +01:00
Thierry Reding
473079549f drm/tegra: dc: Add Tegra186 support
The display architecture has changed in several signifcant ways with the
new Tegra186 SoC. Display controllers are a completely different design,
but have been given a frontend that simulates the register interface for
earlier chips.

Unfortunately the frontend isn't completely backwards compatible, so the
driver needs parameterization to take the changes into account.

One big change is that the total number of display controllers has been
increased to three. At the same time the number of planes available has
remained constant. However, planes can now be freely assigned between
the display controllers, giving applications more flexibility in making
the best use of the available resources.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13 14:16:38 +01:00
Thierry Reding
c4755fb906 drm/tegra: Add Tegra186 display hub support
The display architecture has changed in several significant ways with
the new Tegra186 SoC. Shared between all display controllers is a set
of common resources referred to as the display hub. The hub generates
accesses to memory and feeds them into various composition pipelines,
each of which being a window that can be assigned to arbitrary heads.

Atomic state is subclassed in order to track the global bandwidth
requirements and select and adjust the hub clocks appropriately. The
plane code is shared to a large degree with earlier SoC generations,
except where the programming differs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13 14:16:37 +01:00
Thierry Reding
b1415ff21d drm/tegra: dc: Move state definition to header
Move the display controller state definition to the header file so that
it can be referenced by other files.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13 13:42:22 +01:00
Thierry Reding
9d99ab6e5f drm/tegra: Remove custom page-flip handler
Tegra display hardware has GO bits and meets all the requirements to use
drm_crtc_arm_vblank_event(). Use it instead and get rid of the hand-
rolled implementation.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13 13:42:10 +01:00
Thierry Reding
31b02caea3 drm/tegra: Use atomic commit helpers
There's no reason not to use them, and they already get all the
semantics right, so rip out all of the custom code and replace it by the
helpers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13 13:42:10 +01:00
Thierry Reding
7116e9a802 drm/tegra: dc: Support background color
Starting with Tegra124, the interface to set the background color (the
value generated for pixels that are not sourced from any window) is via
a different register. Earlier generations called this the border color.
Reverse the feature flag and assume that IP revisions that don't have
support for background color will support border color instead.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13 13:42:09 +01:00
Thierry Reding
b95800eeef drm/tegra: dc: Register debugfs in ->late_register()
The ->late_register() and ->early_unregister() callbacks are called at
the right time to make sure userspace only accesses interfaces when it
should. Move debugfs registration and unregistration to these callback
functions to avoid potential races with userspace.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13 13:42:07 +01:00
Thierry Reding
2d1c18fb0d drm/tegra: dc: Move some declarations to dc.h
Move the DC related declarations in drm.h to dc.h where they belong.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-10-20 14:19:54 +02:00
Thierry Reding
459cc2c680 drm/tegra: sor: Add HDMI support
The SOR1 introduced on Tegra210 supports HDMI 2.0 and DisplayPort. Add
HDMI support and name the debugfs node after the type of SOR. The SOR
introduced with Tegra124 is known simply as "sor", whereas the
additional SOR found on Tegra210 is known as "sor1".

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:49:37 +02:00
Thierry Reding
472a6d1fd5 drm/tegra: dc: Rename BASE_COLOR_SIZE* fields
Use an underscore to separate the prefix from the color size suffix.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:43 +02:00
Thierry Reding
8fd3ffa902 drm/tegra: dc: Rename register for consistency
The horizontal pulse enable bits are named H_PULSE{0,1,2}_ENABLE in the
TRM. Modify the driver to use the same naming for consistency.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:43 +02:00
Thierry Reding
6ca1f62f0d drm/tegra: dc: Implement CRC debugfs interface
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:41 +02:00
Thierry Reding
42e9ce0523 drm/tegra: dc: Implement hardware VBLANK counter
The display controller on Tegra can use syncpoints to count VBLANK
events. syncpoints are 32-bit unsigned integers, so well suited as
VBLANK counters.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02 18:46:21 +02:00
Thierry Reding
c134f019ab drm/tegra: Implement more tiling modes
Tegra124 supports a block-linear mode in addition to the regular pitch
linear and tiled modes. Add support for these by moving the internal
representation into a structure rather than a simple flag.

Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-08-04 10:07:34 +02:00
Thierry Reding
e687651bc1 drm/tegra: Add hardware cursor support
Enable hardware cursor support on Tegra124. Earlier generations support
the hardware cursor to some degree as well, but not in a way that can be
generically exposed.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-05 23:14:47 +02:00
Thierry Reding
eba66501ac drm/tegra: dc - Rename INVERT_V to V_DIRECTION
V_DIRECTION is the name of the field in the documentation, so use that
for consistency. Also add the H_DIRECTION field for completeness.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-05 23:09:17 +02:00
Thierry Reding
6b6b604215 drm/tegra: Add eDP support
Add support for eDP functionality found on Tegra124 and later SoCs. Only
fast link training is currently supported.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-04-04 09:12:50 +02:00
Thierry Reding
72d3028615 drm/tegra: Relocate some output-specific code
Some of the code in the CRTC's mode setting code is specific to the RGB
output or needs to be called slightly differently depending on the type
of output. Push that code down into the output drivers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-20 15:56:07 +01:00
Thierry Reding
8620fc629a drm/tegra: Add Tegra124 DC support
Tegra124 and later support interlacing, but the driver doesn't support
it yet. Make sure interlacing stays disabled on hardware that supports
it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-20 15:56:06 +01:00
Thierry Reding
dec727399a drm/tegra: Add DSI support
This commit adds support for both DSI outputs found on Tegra. Only very
minimal functionality is implemented, so advanced features like ganged
mode won't work.

Due to the lack of other test hardware, some sections of the driver are
hardcoded to work with Dalmore.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-20 15:56:04 +01:00
Thierry Reding
db7fbdfd25 drm/tegra: Support bottom-up buffer objects
The gr3d engine renders images bottom-up. Allow buffers that are used
for 3D content to be marked as such and implement support in the display
controller to present them properly.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:55:46 +01:00
Thierry Reding
773af77fc4 drm/tegra: Add support for tiled buffer objects
The gr2d and gr3d engines work more efficiently on buffers with a tiled
memory layout. Allow created buffers to be marked as tiled so that the
display controller can scan them out properly.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:55:46 +01:00
Thierry Reding
dee8268f8f drm/tegra: Move driver to DRM tree
In order to make subsystem-wide changes easier, move the Tegra DRM
driver back into the DRM tree.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:55:40 +01:00
Terje Bergstrom
4231c6b01a drm/tegra: Move drm to live under host1x
Make drm part of host1x driver.

Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Erik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
2013-04-22 12:39:11 +02:00
Thierry Reding
3c03c46ac8 drm/tegra: Implement page-flipping support
All the necessary support bits like .mode_set_base() and VBLANK are now
available, so page-flipping case easily be implemented on top.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
2013-02-22 08:21:27 +01:00
Thierry Reding
f34bc78741 drm/tegra: Add plane support
Add support for the B and C planes which support RGB and YUV pixel
formats and can be used as overlays or hardware cursor. Currently 32-bit
XRGB as well as UYVY, YUV420 and YUV422 pixel formats are advertised.
Other formats should be easy to add but these are the most common ones
and should cover the majority of use-cases.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
2013-02-22 08:21:12 +01:00
Thierry Reding
d8f4a9eda0 drm: Add NVIDIA Tegra20 support
This commit adds a KMS driver for the Tegra20 SoC. This includes basic
support for host1x and the two display controllers found on the Tegra20
SoC. Each display controller can drive a separate RGB/LVDS output.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Mark Zhang <markz@nvidia.com>
Reviewed-by: Mark Zhang <markz@nvidia.com>
Tested-by: Mark Zhang <markz@nvidia.com>
Tested-and-acked-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-11-20 15:43:41 +10:00