When none of the OMAP4-generation SoCs are enabled, we run into a link
error for am43xx/am43xx:
drivers/clk/ti/dpll.o: In function `of_ti_am3_dpll_x2_setup':
dpll.c:(.init.text+0xd8): undefined reference to `clkhwops_omap4_dpllmx'
This is easily fixed by adding another #ifdef.
While looking at the code, I also spotted another problem with the
assignment of hw_ops variable that is not used again later. I'm
changing this to setting clk_hw->ops instead, which I guess is what
was intended here.
Fixes: 473adbf4e0 ("clk: ti: dpll44xx: fix clksel register initialization")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Tero Kristo <t-kristo@ti.com>
[sboyd@codeaurora.org: Replaced fixes tag with correct one]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Currently, TI clock driver uses an encapsulated struct that is cast into
a void pointer to store all register addresses. This can be considered
as rather nasty hackery, and prevents from expanding the register
address field also. Instead, replace all the code to use proper struct
in place for this, which contains all the previously used data.
This patch is rather large as it is touching multiple files, but this
can't be split up as we need to avoid any boot breakage.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
clksel register pointer should be used for the DPLL-MX autoidle handling.
Currently this is not setup at all. Fix by adding proper handling for the
register.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
This has been superceded by the usage of ti_clk_ll_ops for now.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
The OMAP36xx DPLL5, driving EHCI USB, can be subject to a long-term
frequency drift. The frequency drift magnitude depends on the VCO update
rate, which is inversely proportional to the PLL divider. The kernel
DPLL configuration code results in a high value for the divider, leading
to a long term drift high enough to cause USB transmission errors. In
the worst case the USB PHY's ULPI interface can stop responding,
breaking USB operation completely. This manifests itself on the
Beagleboard xM by the LAN9514 reporting 'Cannot enable port 2. Maybe the
cable is bad?' in the kernel log.
Errata sprz319 advisory 2.1 documents PLL values that minimize the
drift. Use them automatically when DPLL5 is used for USB operation,
which we detect based on the requested clock rate. The clock framework
will still compute the PLL parameters and resulting rate as usual, but
the PLL M and N values will then be overridden. This can result in the
effective clock rate being slightly different than the rate cached by
the clock framework, but won't cause any adverse effect to USB
operation.
Signed-off-by: Richard Watts <rrw@kynesim.co.uk>
[Upported from v3.2 to v4.9]
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
max-rate parameter based on the DPLL types.
[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Change the types here to unsigned int instead of int and update
the checks for == 0 instead < 1 to be more explicit about what's
going on now that of_clk_get_parent_count() has changed return
types.
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Convert DPLL support code to use clk_hw pointers for reference and bypass
clocks. This allows us to use clk_hw_* APIs for accessing any required
parameters for these clocks, avoiding some locking problems at least with
DPLL enable code; this used clk_get_rate which uses mutex but isn't
good under clk_enable / clk_disable.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Mostly converted with the following snippet:
@@
struct clk_hw *E;
@@
-__clk_get_flags(E->clk)
+clk_hw_get_flags(E)
Acked-by: Tero Kristo <t-kristo@ti.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* cleanup-clk-h-includes: (62 commits)
clk: Remove clk.h from clk-provider.h
clk: h8300: Remove clk.h and clkdev.h includes
clk: at91: Include clk.h and slab.h
clk: ti: Switch clk-provider.h include to clk.h
clk: pistachio: Include clk.h
clk: ingenic: Include clk.h
clk: si570: Include clk.h
clk: moxart: Include clk.h
clk: cdce925: Include clk.h
clk: Include clk.h in clk.c
clk: zynq: Include clk.h
clk: ti: Include clk.h
clk: sunxi: Include clk.h and remove unused clkdev.h includes
clk: st: Include clk.h
clk: qcom: Include clk.h
clk: highbank: Include clk.h
clk: bcm: Include clk.h
clk: versatile: Remove clk.h and clkdev.h includes
clk: ux500: Remove clk.h and clkdev.h includes
clk: tegra: Properly include clk.h
...
Use of_clk_parent_fill to fill in the parent clock names' array.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This clock provider uses the consumer API, so include clk.h
explicitly.
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/ti/clk.c:125:31: warning: incorrect type in return expression (different address spaces)
drivers/clk/ti/clk.c:125:31: expected void [noderef] <asn:2>*
drivers/clk/ti/clk.c:125:31: got void *
drivers/clk/ti/clk.c:132:31: warning: incorrect type in return expression (different address spaces)
drivers/clk/ti/clk.c:132:31: expected void [noderef] <asn:2>*
drivers/clk/ti/clk.c:132:31: got void *
drivers/clk/ti/dpll.c:180:14: warning: symbol '_get_reg' was not declared. Should it be static?
drivers/clk/ti/fapll.c:624:32: warning: Using plain integer as NULL pointer
drivers/clk/ti/fapll.c:625:31: warning: Using plain integer as NULL pointer
drivers/clk/ti/fapll.c:630:40: warning: Using plain integer as NULL pointer
drivers/clk/ti/clk-dra7-atl.c:158:22: warning: symbol 'atl_clk_ops' was not declared. Should it be static?
drivers/clk/ti/clk-dra7-atl.c:170:39: warning: Using plain integer as NULL pointer
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
There is a case where NULL can be a valid return value for
ti_clk_get_reg_addr, specifically the case where both the provider index
and register offsets are zero. In this case, the current error checking
against a NULL pointer will fail. Thus, change the API to return a
ERR_PTR value in an error case, and change all the users of this API to
check against IS_ERR instead.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
The 'ARM: OMAP3: legacy clock data move under clk driver' patch series
causes build errors when CONFIG_OMAP3 is not set:
drivers/clk/ti/dpll.c: In function 'ti_clk_register_dpll':
drivers/clk/ti/dpll.c:199:31: error: 'omap3_dpll_ck_ops' undeclared (first use in this function)
const struct clk_ops *ops = &omap3_dpll_ck_ops;
^
drivers/clk/ti/dpll.c:199:31: note: each undeclared identifier is reported only once for each function it appears in
drivers/clk/ti/dpll.c:259:10: error: 'omap3_dpll_per_ck_ops' undeclared (first use in this function)
ops = &omap3_dpll_per_ck_ops;
^
drivers/built-in.o: In function `ti_clk_register_gate':
drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_omap3430es2_dss_usbhost_wait'
drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_am35xx_ipss_module_wait'
-in.o: In function `ti_clk_register_interface':
drivers/clk/ti/interface.c💯 undefined reference to `clkhwops_omap3430es2_iclk_hsotgusb_wait'
drivers/clk/ti/interface.c💯 undefined reference to `clkhwops_omap3430es2_iclk_dss_usbhost_wait'
drivers/clk/ti/interface.c💯 undefined reference to `clkhwops_omap3430es2_iclk_ssi_wait'
drivers/clk/ti/interface.c💯 undefined reference to `clkhwops_am35xx_ipss_wait'
drivers/built-in.o: In function `ti_clk_register_composite':
:(.text+0x3da768): undefined reference to `ti_clk_build_component_gate'
In order to fix that problem, this patch makes the omap3 legacy code
compiled only when both CONFIG_OMAP3 and CONFIG_ATAGS are set.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Currently, DPLLs are hiding the gory details of switching parent
within set_rate, which confuses the common clock code and is wrong.
Fixed by applying the new determine_rate() and set_rate_and_parent()
functionality to any clock-ops previously using the broken approach.
This patch also removes the broken legacy code.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
MPU DPLL on OMAP5, DRA75x, DRA72x has a limitation on the maximum
frequency it can be locked at. Duty Cycle Correction circuit is used
to recover a correct duty cycle for achieving higher frequencies
(hardware internally switches output to M3 output(CLKOUTHIF) from M2
output (CLKOUT)).
So provide support to setup required data to handle Duty cycle by
the setting up the minimum frequency for DPLL. 1.4GHz is common
for all these devices and is based on Technical Reference Manual
information for OMAP5432((SWPU282U) chapter 3.6.3.3.1 "DPLLs Output
Clocks Parameters", and equivalent information from DRA75x, DRA72x
documentation(SPRUHP2E, SPRUHI2P).
Signed-off-by: Nishanth Menon <nm@ti.com>
[t-kristo@ti.com: updated for latest dpll init API call]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
OMAP2 has slightly different DPLL compared to later OMAP generations.
This patch adds support for the ti,omap2-dpll-core-clock and also adds
the bindings documentation.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
AMxxxx dpll_data previously had autoidle_mask set, even if these SoC:s
don't have autoidle register. Remove the bit-field value as it is unused,
also drop the unnecessary DPLL_HAS_AUTOIDLE flag passing during init,
as we can just simply check against the contents of the autoidle_mask.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
