2 Commits

Author	SHA1	Message	Date
Sricharan R	f1e8e38114	ARM: dts: doc: Document missing binding for omap5-mpu ... The binding and support for omap5-mpu which has a cortex-a15 smp core, gic and integrated L2 cache has been existing for sometime. So Documenting the missing binding here. Cc: Benoit Cousson <bcousson@baylibre.com> Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com>	2013-12-02 23:35:23 -06:00
Benoit Cousson	476b679a5d	arm/dts: OMAP3+: Add mpu, dsp and iva nodes ... Add nodes for devices used by PM code (mpu, dsp, iva). Add a cpus node as well as recommended in the DT spec. Remove mpu, dsp, iva devices init if is populated. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Cc: Kevin Hilman <khilman@ti.com>	2011-10-04 22:29:40 +02:00