Rename dispc's manager related functions as follows:
- Remove prepending underscores, which were originally used to inform
that the clocks needs to be enabled. This meaning is no longer valid.
- Prepend the functions with dispc_mgr_*
- Remove "channel" from the name, e.g. dispc_enable_channel ->
dispc_mgr_enable
The idea is to group manager related functions so that it can be deduced
from the function name that it writes to manager spesific registers.
All dispc_mgr_* functions have enum omap_channel as the first parameter.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Rename dispc's overlay related functions as follows:
- Remove prepending underscores, which were originally used to inform
that the clocks needs to be enabled. This meaning is no longer valid.
- Prepend the functions with dispc_ovl_*
- Remove "plane" from the name, e.g. dispc_set_plane_ba0 ->
dispc_ovl_set_ba0
The idea is to group overlay related functions so that it can be deduced
from the function name that it writes to overlay spesific registers.
All dispc_ovl_* functions have enum omap_plane as the first parameter.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Add OMAP_DSS_OVL_CAP_GLOBAL_ALPHA and OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA to
overlay capabilities. Use these instead of FEAT_GLOBAL_ALPHA,
FEAT_GLOBAL_ALPHA_VID1 and FEAT_PRE_MULT_ALPHA in code.
Remove FEAT_GLOBAL_ALPHA_VID1 and FEAT_PRE_MULT_ALPHA which are no
longer used. FEAT_GLOBAL_ALPHA is still used to decide if the HW has
global alpha register.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Archit Taneja <archit@ti.com>
Use lookup tables instead of switch/if in some DISPC functions to make
the code cleaner.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Archit Taneja <archit@ti.com>
Remove support for non-DISPC overlays and overlay managers.
The support to possibly have non-DISPC overlays and managers was made to
make it possible to use CPU and/or sDMA to update RFBI or DSI command
mode displays. It is ok to remove the support, because:
- No one has used the feature.
- Display update without DISPC is very slow, so it is debatable if the
update would even be usable.
- Removal cleans up code.
- If such a feature is needed later, it is better implemented outside
omapdss driver.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Archit Taneja <archit@ti.com>
Currently when changing the manager of an overlay, set_manager() directly
calls dispc to set the overlay's destination.
Change this to be more in line with other overlay configurations, and
this will also remove the need to have dispc clocks enabled when calling
set_manager().
A new field is added to overlay struct, "manager_changed". This is
similar to "display_changed" field in manager struct, and is used to
inform apply that the manager has changed and thus write to the
registers is needed.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Now that the HWMOD fmwk handles the fcks of DSS modules properly, the
DSS driver no longer needs to explicitely enable/disable the fck.
This patch removes the enables/disables of fck from dispc, dsi and dss.
The clk_get(fck) is still needed there, as the modules need to know the
frequency of the clock.
For hdmi and venc this patch also removes the clk_get(fck), as they
don't need the clock at all.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
The array size of fifo_size array in the global dispc struct is currently
hardcoded to 3. Replace this with the MAX_DSS_OVERLAYS macro in dss_features.h,
use dss_features function to get the number of overlays instead of the
ARRAY_SIZE macro in dispc_read_plane_fifo_sizes().
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Iterate over overlay id's to shorten _dispc_set_color_conv_coef()
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Iterate over manager and overlay id's to shorten dispc_save_context() and
dispc_restore_context().
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Iterate over manager and overlay id's to shorten dispc_dump_regs().
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Prepare dispc_dump_regs() to iterate over manager and overlay id's. Doing this
requires modifications of the macro "DUMPREG" which currently needs us to specify
the manager/overlay name to get the correct result. For example, in order to
print the register DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD), we can't iterate over
a varaible i and get the desired result through DUMPREG(DISPC_TIMING_H(i)).
Split the registers into 3 sections, the first with no arguments(common
registers), the second with one argument(manager/overlay id), and the third with
two arguments(overlay id and coefficient index), redefine DUMPREG macros for
each of these.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
There's no guarantee that the error handler worker thread
will run while the dispc clocks are on. Explicitly enable/disable
them.
Signed-off-by: Dima Zavin <dima@android.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
The current method of saving and restoring the context could cause a
restore before saving, effectively "restoring" zero values to registers.
Add ctx_valid field to indicate if the saved context is valid and can be
restored.
Also restructure the code to save the ctx_loss_count in save_context(),
which makes more sense than the previous method of storing new
ctx_loss_count in dispc_need_ctx_restore.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
dispc.c enables and disables clocks in almost every function to make
sure the clocks are enabled when the function is called. This is rather
unoptimal way to handle the problem.
With pm_runtime other components have to call dispc_runtime_get() to
enable dispc clocks before calling any other dispc functions. Thus the
finegrained clk enables/disables can be removed.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Use PM runtime and HWMOD support to handle enabling and disabling of DSS
modules.
Each DSS module will have get and put functions which can be used to
enable and disable that module. The functions use pm_runtime and hwmod
opt-clocks to enable the hardware.
Acked-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
The DMA FIFO threshold registers and burst size registers have changed
for OMAP4. The current code only handles OMAP2/3 case, and so the
values are a bit off for OMAP4. A summary of the differences between
OMAP2/3 and OMAP4:
Burst size:
OMAP2/3: 4 x 32 bits / 8 x 32 bits / 16 x 32 bits
OMAP4: 2 x 128 bits / 4 x 128 bits / 8 x 128 bits
Threshold size:
OMAP2/3: in bytes (8 bit units)
OMAP4: in 128bit units
This patch fixes the issue by creating two new helper functions in
dss_features: dss_feat_get_buffer_size_unit() and
dss_feat_get_burst_size_unit(). These return (in bytes) the unit size
for threshold registers and unit size for burst size register,
respectively, and are used to calculate correct values.
For the threshold size the usage is straightforward. However, the burst
size register has different multipliers for OMAP2/3 and OMAP4. This
patch solves the problem by defining the multipliers for the burst size
as 2x, 4x and 8x, which fit fine for the OMAP4 burst size definition
(i.e. burst size unit for OMAP4 is 128bits), but requires a slight twist
on OMAP2/3 by defining the burst size unit as 64bit.
As the driver in practice always uses the maximum burst size, and no use
case currently exists where we would want to use a smaller burst size,
this patch changes the driver to hardcode the burst size when
initializing DISPC. This makes the threshold configuration code somewhat
simpler.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Add Color Phase Rotation (CPR) support and sysfs files to enable CPR and
to set the CPR coefficient matrix.
CPR is enabled via manager?/cpr_enable file, and the coefficient matrix
is set via manager?/cpr_coef file. The values in cpr_coef are in the
following order:
RR RG RB GR GG GB BR BG BB
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
OMAP2 doesn't have CPR, PRELOAD nor FIR_COEF_V registers. Add new
feature definitions for those, and check the feature before accessing
those registers.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
omapdss.h included platform_device.h and atomic.h, neither of which is
needed by omapdss.h. Remove those includes from omapdss.h, and fix the
affected .c files which did not include platform_device.h even though
they should.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Add the support for NV12 color format.
Configure base address for UV component of NV12 color format.
Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling
chroma-resampling for video pipeline and hence using FIR2 register set for
scaling UV.
Changes to _dispc_set_scaling(), because of the reason above, are:
- call _dispc_set_scaling_common() to handle scaling for all color formats
except for OMAP4 where it only handles scaling for RGB or Y-component
- call _dispc_set_scaling_uv() for special handling required for UV
component on OMAP4.
- dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes.
Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by
Lajos Molnar <molnar@ti.com>
Signed-off-by: Amber Jain <amber@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Add new registers specific to UV color component that are introduced in OMAP4.
Add simple helper functions to configure the newly added registers.
These new registers are mainly:
- UV base address registers used specifically for NV12 color-format
- FIR registers used for UV-color-component scaling on OMAP4
- Accumulator registers used for UV-color-component scaling
Add these new registers to save/restore and DUMPREG functions.
Also add two new features for OMAP4:
- FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires
separate handling.
- FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register.
Signed-off-by: Amber Jain <amber@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Use for loop instead of individual entries for OVL_FIR_COEF_H, OVL_FIR_COEF_HV,
OVL_FIR_COEF_V and OVL_CONV_COEF in SR() and RR().
Signed-off-by: Amber Jain <amber@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
FIR values can never be zero as per TRM, and the current code writes zero
when scaling is not used. It was not causing any problem as scaling was
disabled when zero was written. Its still safer to not write zero to
it in any case.
Now we configure correct FIR values even when scaling is not used (i.e. set FIR
to 1024 when scaling is not used), but the scaling enable bits are still kept
off if the scaling is not needed.
Signed-off-by: Amber Jain <amber@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Add new color formats supported by OMAP4: NV12, RGBA16, RGBX16,
ARGB16_1555, XRGB16_1555.
NV12 color format is defined here, its support in DSS will be added separately.
Signed-off-by: Amber Jain <amber@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Introduce DSI2 PLL clock sources needed by LCD2 channel and DSI2 Protocol
engine and DISPC Functional clock. Do the following:
- Modify dss_get_dsi_clk_source() and dss_select_dsi_clk_source() to take the
dsi module number as an argument.
- Create debugfs files for dsi2, split the corresponding debugfs functions.
- Allow DPI to use these new clock sources.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
The DSI interface is represented as a platform device, using the DSI platform
driver(dsi.c). The current DSI driver design is capable of running only one
instance of a DSI device. On OMAP4, there are 2 very similar DSI modules which
can be represented as instances of "omapdss_dsi" platform device.
Add member "module" in "dssdev.phy.dsi" that tells us which DSI module's lanes
the panel is connected to. Modify dsi.c functions to take the device's
platform_device struct pointer, provide functions dsi_get_dsidev_from_dssdev()
and dsi_get_dsidev_from_id() take the panel's omap_dss_device and module number
respectively, and return the platform_device pointer. Currently, the dsi struct
is declared globally and is accessed when dsi data is needed. The new pdev
argument will be used later to provide the platform device's dsi related data.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
struct dispc_reg was originally used while migrating from old omapfb to
catch cases where the arguments to dispc_read_reg/dispc_write_reg were in
wrong order, since old omapfb had the arguments in reverse order.
Remove this struct and use u16 instead
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Represent manager/channel specific DISPC registers as inline functions returning
the required dispc_reg struct. This is done since the current method is not
scalable as the number of overlay managers increase in number.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Move all DISPC register definitions to a new header dispc.h. There are
separate register offset definitions for GFX, VID1 and VID2 pipeline share
register definitions by using an argument. The introduction of VID3 pipeline
on OMAP4 will not let us use the above method since VID3 pipe register offsets
don't map with VID1 and VID2 offsets.
Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument
tells the overlay. Register offsets are calculated as:
DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane)
Idea suggested by Tomi Valkeinen.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Change enum dss_clk_source to omap_dss_clock_source and move it to
'plat/display.h'. Change the enum members to attach "OMAP_" in the beginning.
These changes are done in order to specify the clock sources for DSS in the
board file.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
arch/arm/plat-omap/include/plat/display.h is an include for the OMAP DSS
driver. A more logical place for it is in include/video.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Adding function to reset/set gamma table bit for TV interface, currently
only support for disabled is added.
Signed-off-by: Mythri P K <mythripk@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
On OMAP3, the pixel clock for the LCD manager was derived through DISPC_FCLK as:
Lcd Pixel clock = DISPC_FCLK / lcd / pcd
Where lcd and pcd are divisors in the DISPC_DIVISOR register.
On OMAP4, the pixel clocks for LCD1 and LCD2 managers are derived from 2 new
clocks named LCD1_CLK and LCD2_CLK. The pixel clocks are calculated as:
Lcd_o Pixel clock = LCDo_CLK / lcdo /pcdo, o = 1, 2
Where lcdo and pcdo registers are divisors in DISPC_DIVISORo registers.
LCD1_CLK and LCD2_CLK can have DSS_FCLK, and the M4 divider clocks of DSI1 PLL
and DSI2 PLL as clock sources respectively. Introduce functions to select and
get the clock source for these new clocks. Modify DISPC functions get the
correct lck and pck rates based on the clock source of these clocks. Since
OMAP2/3 don't have these clocks, force OMAP2/3 to always have the LCD_CLK source
as DSS_CLK_SRC_FCK by introducing a dss feature.
Introduce clock source names for OMAP4 and some register field changes in
DSS_CTRL on OMAP4.
Currently, LCD2_CLK can only have DSS_FCLK as its clock source as DSI2 PLL
functionality hasn't been introduced yet. BUG for now if DSI2 PLL is selected as
clock.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Clean up some of the DSS functions which select/get clock sources, use switch
to select the clock source members since more clock sources will be introduced
later on.
Remove the use of macro CONFIG_OMAP2_DSS_DSI in dispc_fclk_rate, use a dummy
inline for function for dsi_get_pll_hsdiv_dispc_rate() instead for code clarity.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Fix handling of error in omap_dispc_register_isr() in case there are no
free isr slots available.
Reported-by: Ben Tucker <btucker@mpcdata.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Using dss_features to select independent core clock divider and setting
it. Added the register used, to DISPC context save and restore group
-----------------------------------------------------------------------
In OMAP4, the minimum DISPC_CORE_CLK required can be expressed as:
DISPC_CORE_CLK >= max(PCLK1*HSCALE1, PCLK2*HSCALE2, ...)
Where PCLKi is the pixel clock generated by MANAGERi and HSCALEi is the
maximum horizontal downscaling done through MANAGERi
Based on the usecase, core clk can be increased or decreased at runtime
to save power. Such mechanism are not yet implemented. Hence, we set the
core clock divisor to 1, to support maximum range of resolutions
------------------------------------------------------------------------
Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR.
However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK
independent of Primary and Secondary display clocks.
Renamed DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch), to facilitate introduction
of DISPC_DIVISOR register, which is specific for OMAP4. OMAP4 has 3 registers
DISPC_DIVISOR, DISPC_DIVISOR1 and DISPC_DIVISOR2.
Also updated, all the usages of DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch).
Use DISPC_DIVISORo(ch) when DISPC_DIVISOR1 or DISPC_DIVISOR2 has to be
configured
OMAP4 TRM uses DISPC_DIVISORo generically to refer to DISPC_DIVISOR1 and
DISPC_DIVISOR2
Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
DSI PLL output clock names have been made more generic. The clock name
describes what the source of the clock and what clock is used for. Some of
DSI PLL parameters like dividers and DSI PLL source have also been made more
generic.
dsi1_pll_fclk and dsi2_pll_fclk have been changed as dsi_pll_hsdiv_dispc_clk
and dsi_pll_hsdiv_dsi_clk respectively. Also, the hsdividers are now named
regm_dispc and regm_dsi instead of regm3 and regm4.
Functions and macros named on the basis of these clock names have also been
made generic.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Clock source names vary across OMAP2/3 and OMAP4, the clock source enum
names have been made generic in the driver, but for purposes of debugging
and dumping clock sources, it is better to preserve the actual TRM name of
the clock.
Introduce a dss feature function 'dss_feat_get_clk_source_name()' which
returns a string with the TRM clock name for the current OMAP in use. The OMAP
specific name is printed along the generic name within brackets.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
The enum members of 'dss_clk_source' have clock source names specific to
OMAP2/3. Change the names to more generic terms such that they now describe
where the clocks come from and what they are used for.
Also, change the enum member names to have "DSS_CLK_SRC" instead of "DSS_SRC"
for more clarity.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Add dss_features and register fields to incorporate changes in DISPC pipelines
between OMAP3 and OMAP4.
Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU
DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF
_dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Currently, the core DSS platform device requests for an irq line for OMAP2 and
OMAP3. Make DISPC and DSI platform devices request for a shared IRQ line.
On OMAP3, the logical OR of DSI and DISPC interrupt lines goes to the MPU. There
is a register DSS_IRQSTATUS which tells if the interrupt came from DISPC or DSI.
On OMAP2, there is no DSI, only DISPC interrupts goto the MPU. There is no
DSS_IRQSTATUS register.
Hence, it makes more sense to have separate irq handlers corresponding to the
DSS sub modules instead of having a common handler.
Since on OMAP3 the logical OR of the lines goes to MPU, the irq line is shared
among the IRQ handlers.
The hwmod irq info has been removed for DSS to DISPC and DSI for OMAP2 and OMAP3
hwmod databases. The Probes of DISPC and DSI now request for irq handlers.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
enum dss_clock structure is replaced with generic names that
could be used across OMAP2420, 2430, 3xxx, 44xx platforms.
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
DSS, DISPC, DSI, RFBI, VENC baseaddr can be obtained from platform_get_resource().
This API in turn picks the right silicon baseaddr from the hwmod database.
So hardcoding of base addr could be removed.
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This patch replaces printk's in the init/probe functions to dev_dbg
for boot time optimization.
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Hwmod adaptation design requires each of the DSS HW IP to be a platform driver.
So a platform_driver for DISPC is created and init exit methods are moved from core.c
to its driver probe,remove. pdev member has to be maintained by its own drivers.
DISPC platform driver is registered from inside omap_dss_probe, in the order desired.
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
A panel connects to one of the overlay managers of DSS through some interface block.
On OMAP4, specifying the type of the display is not sufficient to conclude which manager
the panel should be connected to.
Hence, a new member 'channel' is introduced in omap_dss_device structure to determine
which manager the panel uses. The dss_recheck_connections() called in dss_driver_probe()
uses this channel parameter to set the correct manager to the corresponding omap_dss_device.
The channel parameter is used only once to ensure the correct managers are set for each
panel. The parameter dssdev->manager->id will take care of ensuring that the panel and
then the interface driver configures the correct DISPC channel.
Also, add a new Overlay Manager in manager.c, make other changes needed for LCD2 channel.
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
DISPC_CONFIG bits LCDENABLEPOL, LCDENABLESIGNAL, PCKFREEENABLE and FUNCGATED
have been removed from OMAP4, use dss_features to handle them correctly.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
DISPC functions are modified in order to work when the manager is LCD2.
This includes:
Adding new IRQs specific to LCD2 and their handling.
Provide dumps of the new manager's registers.
Provide dumps of the new manager's clocks.
Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2
which can't be parametrized.
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
