Clearing obj-y, obj-m, obj-n, obj- in each Makefile is
a useless habit.
They are non-exported variables; therefore they are always empty
whenever descending into each subdirectory.
(Moreorver, obj-y and obj-m are also set to empty at the beginning
of scripts/Makefile.build)
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Peter Foley <pefoley2@pefoley.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Michal Marek <mmarek@suse.cz>
Enable devices to signal interrupts via PCI memory cycles.
rev6:
* fix enable/disable typo, Michael Ellerman
rev5:
* fix up ack, enable, and disable for iop13xx_msi_chip
rev4:
* move smp compile fix to separate patch
* use dynamic_irq_init in create_irq()
* hookup mask/unmask routines in iop13xx_msi_chip
rev3:
* change msi.c to use linux/smp.h instead of asm/smp.h
* call dynamic_irq_cleanup at destroy_irq time
rev2:
* destroy_irq did not take the full 128 bits of msi_irq_in_use into account
* added missing '&' for calls to test_and_set_bit and clear_bit
[ebiederm@xmission.com: review comments/suggestions]
[dan.j.williams@intel.com: cleanups/forward port to 2.6-git]
Signed-off-by: Daniel Wolstenholme <daniel.e.wolstenholme@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Eric W. Biederman <ebiederm@xmission.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The tpmi units interface with the SAS controller on iop348.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* architecture specific details are handled in asm/arch/time.h
* ARCH_IOP13XX now selects PLAT_IOP
* as suggested by Lennert use ifdef CONFIG_XSCALE to skip the cp_wait on
XSC3
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a
Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory
controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz
PCI-X interface, a x8 PCI-Express interface, and other peripherals to form
a system-on-a-chip RAID subsystem engine.
The iop342 processor replaces the SAS controller with a second Xscale core
for dual core embedded applications.
The iop341 processor is the single core version of iop342.
This patch supports the two Intel customer reference platforms iq81340mc
for external storage and iq81340sc for direct attach (HBA) development.
The developer's manual is available here:
ftp://download.intel.com/design/iio/docs/31503701.pdf
Changelog:
* removed virtual addresses from resource definitions
* cleaned up some unnecessary #include's
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
