From Dinh Nguyen, this is a series of patches introducing support for
socfpga hardware (Altera Cyclone5). It also includes a cleanup that
moves some of the ARMv7 cache maintenance functions to a common location,
since three other platforms aready implemented it separately.
* socfpga/hw:
arm: socfpga: Add SMP support for actual socfpga harware
arm: Add v7_invalidate_l1 to cache-v7.S
arm: socfpga: Add entries to enable make dtbs socfpga
arm: socfpga: Add new device tree source for actual socfpga HW
Trivial conflict in arch/arm/mach-tegra/headsmp.S.
Signed-off-by: Olof Johansson <olof@lixom.net>
Because the CPU1 start address is different for socfpga-vt and
socfpga-cyclone5, we add code to use the correct CPU1 start addr.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Pavel Machek <pavel@denx.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Tested-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Pavel Machek <pavel@denx.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
Up to this point, support for socfpga has only been on a virtual
platform. Now that actual hardware is available, we add the appropriate
device tree source files.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Tested-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Pavel Machek <pavel@denx.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: Olof Johansson <olof@lixom.net>
This pull request adds initial support for the Tegra114 SoC, which
integrates a quad-core ARM Cortex-A15 CPU. I'm proud to observe that we
posted the initial versions of these patches before the final official
announcement of this chip.
These patches are enough to boot with a UART-based console, support the
Dalmore and Pluto reference/evaluation boards, instantiate the GPIO and
pinctrl drivers, and enable a cpuidle state. As yet, no clocks or
storage devices are supported, but patches for those will follow shortly.
This pull request is based on (most of) the previous pull request with
tag tegra-for-3.9-soc-cpuidle, followed by a merge of the previous pull
request with tag tegra-for-3.9-scu-base-rework.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRCY47AAoJEMzrak5tbycxiCEQAKokAbR2acuzR1BC3o+pQAsv
6/2TkGdZXhgmf7COXkjHLQSnQn5MLSiHSQxVfc8rwpJ7Tma0BaZ1QhoeYKU718ix
S9htYgCurcU6XUuRW6THw3nF1a7S6Z7WX63DS6d1LcGzAHLRAc3Y6Kb1pHCDTThy
Hqf0SvIrpIB6dLpBT63sbbGQjauwd+pvWMFanHwyrKJFOURqMQngzCcXeFqKw8cI
DRS5JWeTZfhOKosnme9lNkWiXM7zYzedtErBcWg3TbtSz8I3DB/I4Zi3lQcwO/hj
K/loW99/tg4mL90FaOtNrO33y1qc/4PAWSLdAvcSs00TvrIPGZ9HULybyY3NYPEK
48XT/3WAS7NtD42MA78DbBDyX4sw2vIz7LZLdTukG/gjIckOE4oapIq4QvIK6OwM
9GkYe8Zx6kASVEKQEntW3iax/VyhU04xpmCYpAVcUkBW260zbHPA95Ltqr6R4vdq
HKezEUq7Gq/kLiiMlnUcotaZY6MHyTOR1SXBN3ai71pAQzhsrHUPOQZoxvoERW7Q
vIN7unQ4lqgmBY4mUnPvFB0pXQ7Y939EGtYK59s7uuQraVe3TI0G/KUlKwbxVzDX
iTtkeu54bfla39kxMaYVUzNhy0mh/TA8PonefgYqZW7QPw4PhfgzYItzOvU6g/XC
cDSQluEEjqwn1vfSBaI1
=bIIe
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.9-soc-t114' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From Stepen Warren:
ARM: tegra: add Tegra114 SoC support
This pull request adds initial support for the Tegra114 SoC, which
integrates a quad-core ARM Cortex-A15 CPU. I'm proud to observe that we
posted the initial versions of these patches before the final official
announcement of this chip.
These patches are enough to boot with a UART-based console, support the
Dalmore and Pluto reference/evaluation boards, instantiate the GPIO and
pinctrl drivers, and enable a cpuidle state. As yet, no clocks or
storage devices are supported, but patches for those will follow shortly.
This pull request is based on (most of) the previous pull request with
tag tegra-for-3.9-soc-cpuidle, followed by a merge of the previous pull
request with tag tegra-for-3.9-scu-base-rework.
* tag 'tegra-for-3.9-soc-t114' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (24 commits)
ARM: DT: tegra114: add pinmux DT entry
ARM: DT: tegra114: add GPIO DT entry
ARM: tegra114: select PINCTRL for Tegra114 SoC
ARM: tegra: add Tegra114 ARM_CPUIDLE_WFI_STATE support
ARM: tegra: Add SMMU entry to Tegra114 DT
ARM: tegra: add AHB entry to Tegra114 DT
ARM: tegra: Add initial support for Tegra114 SoC.
ARM: dt: tegra114: Add new board, Pluto
ARM: dt: tegra114: Add new board, Dalmore
ARM: dt: tegra114: Add new SoC base, Tegra114 SoC
ARM: tegra: fuse: Add chip ID Tegra114 0x35
ARM: OMAP: Make use of available scu_a9_get_base() interface
ARM: tegra: Skip scu_enable(scu_base) if not Cortex A9
ARM: Add API to detect SCU base address from CP15
ARM: tegra: Use DT /cpu node to detect number of CPU core
ARM: tegra: Add CPU nodes to Tegra30 device tree
ARM: tegra: Add CPU nodes to Tegra20 device tree
ARM: perf: simplify __hw_perf_event_init err handling
ARM: perf: remove unnecessary checks for idx < 0
ARM: perf: handle armpmu_register failing
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Remove/add conflict in arch/arm/mach-tegra/common.c resolved.
Remove/remove conflict in arch/arm/mach-tegra/platsmp.c. Leave the empty
stub function for now since removing it in the merge commit is confusing;
will be cleaned up in a separate commit. # # It looks like you may be
committing a merge. # If this is not correct, please remove the file #
.git/MERGE_HEAD # and try again.
The Tegra USB driver has a number of issues:
1) The PHY driver isn't a true platform device, and doesn't implement
the standard USB PHY API.
2) struct device instance numbers were used to make decisions in the
driver, rather than being parameterized by DT or platform data.
This pull request solves issue (2), and lays the groundwork for solving
issue (1). The work on issue (1) involved introducing new DT nodes for
the USB PHYs, which in turn interacted with the Tegra common clock
framework changes, due to the move of clock lookups into device tree.
Hence, these USB driver changes are taken through the Tegra tree with
acks from USB maintainers.
This pull request is based on the previous pull request, with tag
tegra-for-3.9-soc-ccf.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRCYlsAAoJEMzrak5tbycxbp8QANOIUl1AD5R9wyHucs3O4RVN
xKzI0ch2N4lb8dRBNn5oZ/T0fU5m3Y2w+cAJD9INQZaiqbMsGjm7wcJeuy8IUbQL
cjBwYFOySCAIfRJZtLIYax+sB7/Eoa+un2SHtmWJPn/dWrPcJOp1wc+iNJHxVTLu
4kHgG1Rq3A7etorPmvaf5HkATmOKvzXoxrO9LyGdr3/dgEUDa50p4JBRC4V7osFy
Va9B4fOq777/k1aR59SMKOwLoVvw/u+YwYIMStmAflLnWduXRUbA400mc+nDVH+x
66r3JUZ5/0vzyMsLW8AnhbZWfAROedl4JfT9ZYVvsQmxSzIoyQl2dtt1GiDr7/j+
LSWgPT9BaY+masNiwxoFMMqLg+w0RUxkCGmVu0yYGK3xNmuSI9zeZxV+o3oPkyjQ
/IrOerPE45rd8EACBF9hRLI3mc6+kbS2RPXRl74jre7KHAzumVfZrsNb5M5ZbK1z
8h8ucs/7b62YgCTUhYvbWlvBFgcANq2N9r/AJF4TMMIWtpliHDOHGLu0V1Kd2r8c
hWsAB9dgaljcVV7rFXJhjlCJp7U6MkPmKi1lWg9jpYS5nDcCy5smOH1EEYzN6xS8
4e/YLgz/qkChW4cbQQNMRsLhjD+7ouHryTDLNmOZ/n1Rty8mFOqaQsRPl3OA/4DN
jPmL9AneLq4RM44Zdxe5
=8pTe
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.9-soc-usb' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From Stephen Warren:
ARM: tegra: USB driver cleanup
The Tegra USB driver has a number of issues:
1) The PHY driver isn't a true platform device, and doesn't implement
the standard USB PHY API.
2) struct device instance numbers were used to make decisions in the
driver, rather than being parameterized by DT or platform data.
This pull request solves issue (2), and lays the groundwork for solving
issue (1). The work on issue (1) involved introducing new DT nodes for
the USB PHYs, which in turn interacted with the Tegra common clock
framework changes, due to the move of clock lookups into device tree.
Hence, these USB driver changes are taken through the Tegra tree with
acks from USB maintainers.
This pull request is based on the previous pull request, with tag
tegra-for-3.9-soc-ccf.
* tag 'tegra-for-3.9-soc-usb' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
usb: host: tegra: make use of PHY pointer of HCD
ARM: tegra: Add reset GPIO information to PHY DT node
usb: host: tegra: don't touch EMC clock
usb: add APIs to access host registers from Tegra PHY
USB: PHY: tegra: Get rid of instance number to differentiate PHY type
USB: PHY: tegra: get rid of instance number to differentiate legacy controller
ARM: tegra: add clocks properties to USB PHY nodes
ARM: tegra: add DT nodes for Tegra USB PHY
usb: phy: remove unused APIs from Tegra PHY.
usb: host: tegra: Resetting PORT0 based on information received via DT.
ARM: tegra: Add new DT property to USB node.
usb: phy: use kzalloc to allocate struct tegra_usb_phy
ARM: tegra: remove USB address related macros from iomap.h
Tegra already supports the common clock framework, but had issues:
1) The clock driver was located in arch/arm/mach-tegra/ rather than
drivers/clk/.
2) A single "Tegra clock" type was implemented, rather than separate
clock types for PLL, mux, divider, ... type in HW.
3) Clock lookups by device drivers were still driven by device name
and connection ID, rather than through device tree.
This pull request solves all three issues. This required some DT changes
to add clocks properties, and driver changes to request clocks more
"correctly". Finally, this rework allows all AUXDATA to be removed from
Tegra board files, and various duplicate clock lookup entries to be
removed from the driver.
This pull request is based on the previous pull request, with tag
tegra-for-3.9-cleanup.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRCYtBAAoJEMzrak5tbycxKb8P/0cXt2X7mPfoApWV96bI2c9h
VE1wZYREcq0Au3hiNuMmPp1Nwous2zvrXRKXMvLoQi42KwpvZlFjlyn8+xACKmxO
okSJ+aXETzlGh85l5RlnFJMgq181Kn0nDhN5Iwy0FUEJ8/oqdS8fEz5mwQlHflX1
CLaquDVr/edr8LffvsFlxtSmeYNvZ2jYkSgroWeDhVR5Np1/LUCyh5y3edjVl/es
B0/keuZ2fnYZnEfqLTpBEARYDBimymuu8gIoHK5nvtz3d/GGu92sVeda4LuHt8eH
1N+f41ceDR2JG/MIJbLr6PGYmCkAGSM/5Vcfa33G+A7GQT0EVb8jLozGCdrCjaEG
OM33pN5wtv1M9gTLR9swITBWhbTpRWaHnXeZQF7ttaV8dvr/fuOzWBw47k8Jw0FJ
zjGta66kwW7WkT3HDNoM2RRzm9dlJr1xdHOzAaVJnX3VHtHcIvYzDi90Xv9Nn46D
E/qIpExmL4rMrb2+4MxT9CdbfzdBSmsnlRFoWZTIM1NPxA/97i7oAyYVAJ34LCNx
xWqwimhXK14LzGffpSHm9CSz8DHNbehDZRMQD0jGYMn61PFtDB+E/oEq5AEqneuC
KDht3Qdx/mPzJQPE8WV3d5FxeXfXDjj203x/i6x8TOdH8Bt4aoK9ajvPYBpA+2aE
4fPJIobLHGYN/F+GF1VJ
=s9hz
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.9-soc-ccf' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From Stephen Warren:
ARM: tegra: Common Clock Framework rework
Tegra already supports the common clock framework, but had issues:
1) The clock driver was located in arch/arm/mach-tegra/ rather than
drivers/clk/.
2) A single "Tegra clock" type was implemented, rather than separate
clock types for PLL, mux, divider, ... type in HW.
3) Clock lookups by device drivers were still driven by device name
and connection ID, rather than through device tree.
This pull request solves all three issues. This required some DT changes
to add clocks properties, and driver changes to request clocks more
"correctly". Finally, this rework allows all AUXDATA to be removed from
Tegra board files, and various duplicate clock lookup entries to be
removed from the driver.
This pull request is based on the previous pull request, with tag
tegra-for-3.9-cleanup.
* tag 'tegra-for-3.9-soc-ccf' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (31 commits)
clk: tegra30: remove unused TEGRA_CLK_DUPLICATE()s
clk: tegra20: remove unused TEGRA_CLK_DUPLICATE()s
ARM: tegra30: remove auxdata
ARM: tegra20: remove auxdata
ASoC: tegra: remove auxdata
staging: nvec: remove use of clk_get_sys
ARM: tegra: paz00: add clock information to DT
ARM: tegra: add clock properties to Tegra30 DT
ARM: tegra: add clock properties to Tegra20 DT
spi: tegra: do not use clock name to get clock
ARM: tegra: remove legacy clock code
ARM: tegra: migrate to new clock code
clk: tegra: add clock support for Tegra30
clk: tegra: add clock support for Tegra20
clk: tegra: add Tegra specific clocks
ARM: tegra: define Tegra30 CAR binding
ARM: tegra: define Tegra20 CAR binding
ARM: tegra: move tegra_cpu_car.h to linux/clk/tegra.h
ARM: tegra: add function to read chipid
ARM: tegra: fix compile error when disable CPU_IDLE
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Conflicts:
arch/arm/mach-tegra/board-dt-tegra20.c
arch/arm/mach-tegra/board-dt-tegra30.c
arch/arm/mach-tegra/common.c
arch/arm/mach-tegra/platsmp.c
drivers/clocksource/Makefile
- use rtc-mv in mvebu armv7 SoCs
- add pci-e hotplug for kirkwood
Depends on:
- tags/mvebu_fixes_for_v3.8-rc6
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
iQEcBAABAgAGBQJRCqOnAAoJEAi3KVZQDZAewlUH/04tpMdf2rvgNP8uUVPVx62T
cXMga9qLTyXQ9hn31KP7fd/JPLRJFsG/+jy4x687EurJGIXXaWGNadjlE69DEPAZ
jt78sPa+Mo/xYD4XoNCr/ng1cbnTwc1ebSRSfN+nIjWynE8Do7tkOKxfJodTgQCM
XbE3EHfvAktKfJTsFDPsFwoIycEYxFsN4jQPwiCdPHVb24py3FWBy+qep7wtLfSO
gTnakEcOsQc7aFzrFdZ1ZnQ9KRlBYXVN636o4sQkM+UM9Vf7FAWBM4OCi2KP4trU
IlTzknoMAMYat+AtYzq1FcDmajeP/EgG6DbQh7lqUK0LEILn2rdAUlgN2QB3VIs=
=6oef
-----END PGP SIGNATURE-----
Merge tag 'drivers_for_v3.9' of git://git.infradead.org/users/jcooper/linux into next/soc
From Jason Cooper:
mvebu drivers for v3.9
- use rtc-mv in mvebu armv7 SoCs
- add pci-e hotplug for kirkwood
Depends on:
- tags/mvebu_fixes_for_v3.8-rc6
* tag 'drivers_for_v3.9' of git://git.infradead.org/users/jcooper/linux:
cpuidle: kirkwood: Move out of mach directory
rtc: Add support of rtc-mv for MVEBU SoCs
ARM: Kirkwood: Support basic hotplug for PCI-E
arm: mvebu: i2c come back in defconfig
arm: plat-orion: fix printing of "MPP config unavailable on this hardware"
Dove: activate GPIO interrupts in DT
* Changes to allow unplugging of CPU0 by Ulrich Hecht.
* Changes to add reg and device_type properties to cpus
device trees entries by Simon Horman.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRCgzaAAoJENfPZGlqN0++tgEP/RxzNKMXnJ6h6125DD8clPOj
ss8A10YEMlnJX7jtBVrKJeS2RQcsuAHkQ5wojOb/DqZQf5OeVO90n4JotNO9g9F6
cFMq/E6UEGK1zLZ+uauoexbQvVv6pPVL06aSncoVElrhSiu+509aybb5jHALNouc
BrJXzgSyJMlSgL//sqZYtuQraAZo4IWeyzwF8giJs4seyb39JhW5J3uEbCVFklyW
G4qLvoU3z95k96J70YhYYNrNE/1FezzEQyOrns1MnirGsohTn1XSuyt3jzaBzgyI
kMFBo1lYByOed9Qcysv+lUQgA2jO2vJ7VX0PQI20SGDHwzUu8J272Nq54se6gX9M
TKQbYg9LqvfE/He5H9AuIcnpHiVrYArIoGAE2gPsr/NEnGVVwEnCqF87gNe1NDWk
OIpeCbt3AuN4fae+C1G5ohXFmTTndrHybZZfjb5Jd3ty282gbER64MubiK9Kfocj
0KC0IS/Emz5TK/2CsBTq2uSFFG0SlNZw4JcIgH4EjWE71++dSYQwVWrucaB5JEps
q8EZWQd1JwRp0KehJN6MgpLMyG3ilFnErEC1O8U9iKcgxFVyLXB05fG2e5Yn6IBp
eoXVOxPvJpLQJlBvJ7mNIyykSs+txuerUyC3WlIRa6gjiEf95e9y2gca4pYcNesk
ED4IZ2whWihxC9HsI7nC
=l7OU
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc2-for-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
From Simon Horman:
Second round of Renesas ARM-based SoC changes for v3.9
* Changes to allow unplugging of CPU0 by Ulrich Hecht.
* Changes to add reg and device_type properties to cpus
device trees entries by Simon Horman.
* tag 'renesas-soc2-for-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: mach-shmobile: sh73a0: allow unplugging of CPU0
ARM: mach-shmobile: add shmobile_cpu_disable_any()
ARM: mach-shmobile: emev2: Add reg and device_type properties to cpus
ARM: mach-shmobile: sh73a0: Add reg and device_type properties to cpus
Signed-off-by: Olof Johansson <olof@lixom.net>
- add missing gpio interrupt lines to dove dt
- fix bad logic for printing MPP error message on orion boards
- build proper serial port driver after changing mvebu DT compatible property
- This is a change to mvebu_defconfig that I wouldn't usually push out as a
fix. However, the commit
b24212f arm: mvebu: Use dw-apb-uart instead of ns16650 as UART driver
changed the serial driver for the board in the dts file. without the patch
I've included in this pull, users won't see any log messages.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
iQEcBAABAgAGBQJRB+cvAAoJEAi3KVZQDZAej/MH/2eWE2N3eTs8PRshCUoEIQxd
4uConsKhPiIyNK1rHePGI4EY/M07yxYRO7/55ajK5J3NiqxO7N8n0RYIMFsgNoC9
LCPpi2Ts6Rpj87jqj7ION6pfCiIDPE+Lj4hNQAVTuQAMrh04UqaDLHwpfQztETxW
C6X9A8ae+fVFfVQN0AusStImklxv5hf4odUhqvSKd6gy6n20KtV4EQQN+t+OLSgx
IsRUVww6cfqYFNYDWhyWg8SLppIp9m44hluS8f/wPT9zh5Wf6XWnvAZz41cqaf44
FpzURzHQGcmetqPv/MWL9YSCMTSmBxLfW4totTq2wgldl6qQc7bJsF3R0HlsUgc=
=EA67
-----END PGP SIGNATURE-----
Merge tag 'tags/mvebu_fixes_for_v3.8-rc6' into mvebu/drivers
fixes for v3.8-rc6
- add missing gpio interrupt lines to dove dt
- fix bad logic for printing MPP error message on orion boards
- build proper serial port driver after changing mvebu DT compatible property
- This is a change to mvebu_defconfig that I wouldn't usually push out as a
fix. However, the commit
b24212f arm: mvebu: Use dw-apb-uart instead of ns16650 as UART driver
changed the serial driver for the board in the dts file. without the patch
I've included in this pull, users won't see any log messages.
Tegra114 has the GPIO controllers with 8 GPIO bank and each bank
supports 32 pins.
Add DT entry for GPIO controller. Tegra114 GPIO controller is
compatible with Tegra30 GPIO controller driver.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
From Simon Horman, a series of SoC updates for shmobile.
* 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7779: scif .irqs used SCIx_IRQ_MUXED()
ARM: mach-shmobile: sh73a0: Initialise MMCIF using DT
ARM: mach-shmobile: sh73a0: Minimal setup using DT
ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DT
ARM: SH-Mobile: sh73a0: Add CPU Hotplug
ARM: SH-Mobile: sh73a0: Secondary CPUs handle own SCU flags
ARM: shmobile: r8a7740: Add CPU sleep suspend
ARM: shmobile: sh73a0: Add CPU sleep suspend
ARM: shmobile: add function declarations for sh7372 DT helper functions
ARM: sh7372: fix cache clean / invalidate order
ARM: sh7372: add clock lookup entries for DT-based devices
ARM: mach-shmobile: sh73a0 external IRQ wake update
ARM: shmobile: sh73a0: fixup div4_clks bitmap
ARM: shmobile: r8a7740: add TMU timer support
ARM: shmobile: Remove duplicate inclusion of dma-mapping.h in setup-r8a7740.c
Signed-off-by: Olof Johansson <olof@lixom.net>
Fix trivial conflict in board_bcm due to Simon resolving the same conflict
with one less line of whitespace. Keeping end result common with what
we already have in arm-soc.
Conflicts:
arch/arm/mach-bcm/board_bcm.c
As reset GPIO information is PHY specific detail, adding
it to PHY DT node.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add a new evaluation board, Pluto for Tegra 114 family.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add a new evaluation board, Dalmore for Tegra 114 family.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Initial support for Tegra 114 SoC. This is expected to be included in
the board DTS files, Tegra 114 SoC based evaluation board family.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The patch to add USB PHY nodes to device tree was written before Tegra
supported the clocks property in device tree. Now that it does, add the
required clocks properties to these nodes.
This will allow all clk_get_sys() calls in tegra_usb_phy.c to be replaced
by clk_get(phy->dev, clock_name), as part of converting the PHY driver to
a platform driver.
Acked-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add DT nodes for Tegra USB PHY along with related documentation.
Also added a phandle property to controller DT node, for referring
to connected PHY instance.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
As Tegra USB host driver is using instance number for resetting
PORT0 twice, adding a new DT property for handling this.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add clock information to device nodes.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: added second clock to 3d node]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The device tree binding models Tegra30 CAR (Clock And Reset)
as a single monolithic clock provider.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: fixed typo in binding doc]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The Tegra20 CAR (Clock And Reset) Controller controls most aspects of
most clocks within Tegra20. The device tree binding models this as a
single monolithic clock provider, which exports many clocks. This reduces
the number of nodes needed in device tree to represent these clocks.
This binding is only useful for Tegra20; the set of clocks that exists on
Tegra30 is sufficiently different to merit its own binding.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
[pgaikwad: Added mux clk ids and sorted CAR node]
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add CPU node for Tegra30.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add CPU node for Tegra20.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Mostly clock related updates, most notably the conversion of
i.MX31 to a DT based lookup.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABCAAGBQJRAlqyAAoJEPFlmONMx+ezY8IP/20XCxrkzeCJK04OuyzPRDBS
ejxD/fDjQyw5fArzHZgK5lIG1rhGOmeSdbG/8xlYpBqgzPOZtdd7NlNZvqkLo+Cq
Mu0SLTNM9zY9ibA8vGbyFUEqMX3iKL9Gk6zm3yu/DGX7WqyhObNQhN0yfvgySBJ9
fsQD1BEzm0U60BKiumbNH+sHNSDR6ZTB0Q3lbE42GwUqOax9c6ObrqibB+LRyNDd
7WkwkyhFSXG8MyBfLtIw4HorinewGEdwKZ2GSY/QstADKkWpA0qW7IXtCfk76sRy
8E018twHCpRT9wK6UEWIxDj7qLiEEDJsCHsxGaxFP8dRnOM0+Q96idVlI4Uyqwxz
UbHjIf9XuSXfosJrt4bAE4dLfUHndCFmeU99lOOXefnpFghlgPQFYltOZGaUs5YF
BP+j/AV3L0ElyXPFAz2qVEYpcwJjZF0Ik9Ph0AuZva5aifC2g4dRdJ7W9TRmVul/
louSSrMrIFZcDokUchisfJED10Ln4nmKQ5SS5iRa+TYa3Two25kDtQeetouPRzqt
E4MOsf9AcTT2in2ojvQ27ZpaEzYIHjfPkfrV7POMbm+hTTTzoHlJq1ZOIlj4ENxQ
pL3SP7s07neY/9XnaAvuJQTQqihquBXjrrhEDUfobspBnHV/SBRr7AZyATYgouyY
oCfCcrRNm6NBj+aecbEP
=bWtE
-----END PGP SIGNATURE-----
Merge tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc
From Sascha Hauer:
ARM i.MX SoC updates for next
Mostly clock related updates, most notably the conversion of
i.MX31 to a DT based lookup.
* tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6:
ARM: clk-imx35: Fix build warnings with W=1
ARM: imx27: add a clock gate to activate SPLL clock
ARM: mx31: Replace clk_register_clkdev with clock DT lookup
ARM: clk-imx31: Add dummy clock
ARM: Let CONFIG_MACH_IMX31_DT be built by default
Signed-off-by: Olof Johansson <olof@lixom.net>
From Barry Song, this adds support for a new SoC from CSR; marco. It's
SMP, uses GIC instead of VIC and in general needs a bit of rework of
the platform code for setup, which this branch contains.
* 'marco-timer-cleanup-rebase' of git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel:
ARM: PRIMA2: provide two DEBUG_LL ports for prima2 and marco
ARM: PRIMA2: add new SiRFmarco SMP SoC infrastructures
ARM: PRIMA2: irq: make prima2 irq can work even we enable GIC for Marco
ARM: PRIMA2: rtciobg: it is also compatible with marco
ARM: PRIMA2: rstc: enable the support for Marco
ARM: PRIMA2: mv timer to timer-prima2 as we will add timer-marco
ARM: PRIMA2: initialize l2x0 according to mach from DT
ARM: PRIMA2: enable AUTO_ZRELADDR for SIRF in Kconfig
ARM: PRIMA2: add CSR SiRFmarco device tree .dts
Signed-off-by: Olof Johansson <olof@lixom.net>
Similarly as it was done for mx6q, use a DT lookup in order to make maintainance
task for the clock devices easier.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This device also requires a voltage regulator which
should be defined in a board-specific maner. An example
dts snipped follows.
/ {
fixedregulator1v8: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
&mmcif {
vmmc-supply = <&fixedregulator1v8>;
vqmmc-supply = <&fixedregulator1v8>;
};
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Allow a minimal setup of the sh73a0 SoC using a flattened device tree.
In particular, Configure the i2c controllers using a flattened device tree.
SCI serial controller and CMT clock source, whose drivers do not yet
support configuration using a flattened device tree, are still configured
using C code in order to allow booting of a board with this SoC.
*** Please note that the clock initialisation scheme used in
this patch does not currently work with SMP as there
is a yet to be resolved lock-up in workqueue initialisation.
CONFIG_SMP must be disabled when using this code. ***
Includes update from Thierry Reding to no longer use gic_handle_irq()
Cc: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
fix
This allows the GIC interrupt controller of the sh73a0 SoC to be
initialised using a flattened device tree blob.
It does not allow the INTC interrupt controller which is also present on
the sh73a0 SoC to be enabled via device tree. Nor does it handle sharing
of interrupts between the GIC and INTC interrupt controllers.
This limits the usefulness of this code to applications which only wish to
access devices which use interrupts that can be handled by the GIC
interrupt controller. Other applications should, for now, continue using
non-device tree initialisation of the sh72a0 interrupt controllers.
Includes update to use irqchip_init() by Thierry Reding
Cc: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
From Pawel Moll:
- makes the V2P-CA15_A7 (a.k.a. TC2) work with 3.8 kernels
- improves vexpress-sysreg.c behaviour on arm64 platforms
* 'vexpress/fixes' of git://git.linaro.org/people/pawelmoll/linux:
mfd: vexpress-sysreg: Don't skip initialization on probe
ARM: vexpress: Enable A7 cores in V2P-CA15_A7's Device Tree
ARM: vexpress: extend the MPIDR range used for pen release check
One RM9200 setup option is the only C code change.
Some documentation changes can clarify the pinctrl use.
Then, some defconfig modifications are allowing the affected platforms
to boot.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJRAPnqAAoJEAf03oE53VmQbeUH/04lzIgUv63RX2zQFD6Fi1zD
IeYBhfzeSP65CPMqyFnw+lrHUdCWn0JYdFM6/x7J8n1k2+SY3T7N95k5oXlnqO6e
pT/XGontWQIZkyL0jkrawbs5QtE0OYnkm8Ge97qlhul4XoIiyWLFFGDHE36dzcv/
K4FPrG9PVVhjFIiZB+v5I3CnhzLWJvozn9J2ceIZ5d0Z9dwLuHWgXGu6OM2ZRvOw
LR1r2YpnGTKUT0am6tmWm1W7PY6ZQOQXmx5qX/H2X6gRQdq690baYUTOYPK3ZckX
kdEa+pCOQHY1GgimFzUzAVfoCyYwllo1yAWaK2a4qR4kxcaeGd1BYqlKeCFIfRc=
=aKwA
-----END PGP SIGNATURE-----
Merge tag 'at91-fixes' of git://github.com/at91linux/linux-at91 into fixes
From Nicolas Ferre:
Here are fixes for AT91 that are mainly related to device tree.
One RM9200 setup option is the only C code change.
Some documentation changes can clarify the pinctrl use.
Then, some defconfig modifications are allowing the affected platforms
to boot.
* tag 'at91-fixes' of git://github.com/at91linux/linux-at91:
ARM: at91/dts: correct comment in at91sam9x5.dtsi for mii
ARM: at91/at91_dt_defconfig: add at91sam9n12 SoC to DT defconfig
ARM: at91/at91_dt_defconfig: remove memory specification to cmdline
ARM: at91/dts: add macb mii pinctrl config for kizbox
ARM: at91: rm9200: remake the BGA as default version
ARM: at91: fix gpios on i2c-gpio for RM9200 DT
ARM: at91/at91sam9x5 DTS: add SCK USART pins
ARM: at91/at91sam9x5 DTS: correct wrong PIO BANK values on u(s)arts
ARM: at91/at91-pinctrl documentation: fix typo and add some details
As the kernel is able to cope with multiple clusters,
uncomment the A7 cores in the Device Tree for V2P-CA15_A7
tile, making all 5 cores available to the user.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
- fix memory leak in mvebu/clk-cpu.c
- use devm_ to correct/simplify error paths in mvsdio
- add missing #interrupt-cells property in kirkwood
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
iQEcBAABAgAGBQJQ/zvKAAoJEAi3KVZQDZAebCIIAKCaI3zYiHku7Q52Auzog0oU
7Gk6/TpZtolZURusjSVo8ZPWoZhJc9SoFAVkVJPcB9j1xTl3K7iNVOj4DVvi66o2
R8dw85nTKryBc6kapiJEpQhJof9dQKzmNSL36TNLaHjPef/hz3gVn/QqOxmyuBro
ZZI0aUm+idgaDFkQCuevcfuStQGaKdOsIr23QEbicTj0rbgy0OIKrQ2KxFGKnr0Z
YYYjUr9M5wk1mSOsssEcE/a97eejHS201JhYvCfxSpWCjbwiaErg0fzns7wZ2hhV
BKGAEs+M67gcaHR/Pi2fy3LNLtwIcVNNgFYF3aCiBEFQ+hqtar6O9zqSmlBk1bI=
=xOtK
-----END PGP SIGNATURE-----
Merge tag 'mvebu_fixes_for_v3.8-rc5' of git://git.infradead.org/users/jcooper/linux into fixes
From Jason Cooper:
mvebu fixes for v3.8-rc5
- fix memory leak in mvebu/clk-cpu.c
- use devm_ to correct/simplify error paths in mvsdio
- add missing #interrupt-cells property in kirkwood
* tag 'mvebu_fixes_for_v3.8-rc5' of git://git.infradead.org/users/jcooper/linux:
ARM: kirkwood: fix missing #interrupt-cells property
mmc: mvsdio: use devm_ API to simplify/correct error paths.
clk: mvebu/clk-cpu.c: fix memory leakage
In a DT, the interrupts of an interrupt-controller are not usable when
#interrupt-cells is missing.
This patch activates the interrupts of the GPIOs 0 and 1 for the Marvell
Dove SoC.
Signed-off-by: Jean-François Moine <moinejf@free.fr>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Concerning pinctrl_macb0_rmii_mii, values were okay, but not comments.
Signed-off-by: Douglas Gilbert <dgilbert@interlog.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This patch overrides default macb pinctrl config defined in
at91sam9260.dtsi (pinctrl_macb_rmii) with kizbox board config
(pinctrl_macb_rmii + pinctrl_macb_rmii_mii_alt).
Signed-off-by: Boris BREZILLON <linux-arm@overkiz.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The SCK pins where missing in usarts pinctrl.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The PIN_BANK 3 is for PDxx pins, not PCxx pins.
And PIN_BANK 1 is for PBxx, not PIN_BANK 0.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The gpio controller on kirkwood can provide interrupts but is missing
the #interrupt-cells property. This patch just adds it to both gpio
controllers.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
