Since MDSS registers were stuffed within the the MDP5 register
space, we had an __offset_MDP() macro to identify the offset
between the start of MDSS and MDP5 address spaces. This offset
macro expected a MDP index argument, which didn't make much
sense since we don't have multiple MDPs.
The offset is no longer needed now that we have devices for the 2
different register address spaces. Also, remove the "REG_MDP5_MDP_"
prefix to "REG_MDP5_".
Update the generated headers in mdp5.xml.h
We generally update headers as a separate patch, but we need to
do these together to prevent breaking build.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
With the new kms_init/destroy funcs in place for MDP5, we can get rid of
the old kms funcs. Some members of the mdp5_kms struct also become
redundant, so we remove those too.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Call msm_mdss_init in msm_drv to set up top level registers/irq line.
Start using the new kms_init2/destroy2 funcs to inititalize MDP5 KMS.
With the MDSS interrupt and irqdomain set up, the old MDP5 irq code
can be dropped.
The mdp5_hw_init kms func now uses the platform device tied to MDP5
instead of the one tied to the drm_device/MDSS.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
With MDP5 as a new device, we need to do less for MDP when initializing
modeset after all the components are bound.
Create mdp5_kms_init2/destroy2 funcs that inits modeset. These will
eventually replace the older kms_init/destroy funcs.
In the new kms_init2, the platform_device used is the one corresponding
to the new MDP5 platform_device. The new change here is that the irq is
now retrieved using irq_of_parse_and_map(), since MDP5 is a child interrupt
of the MDSS interrupt controller.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
In order to have a tree-like device hierarchy between MDSS and its
sub-blocks (MDP5, DSI, HDMI, eDP etc), we need to create a separate
device/driver for MDP5. Currently, MDP5 and MDSS are squashed
together are are tied to the top level platform_device, which is
also the one used to create drm_device.
The mdp5_kms_init code is split into two parts. The part where device
resources are allocated are associated with the MDP5 driver's probe,
the rest is executed later when we initialize modeset.
With this change, unlike MDP4, the MDP5 platform_device isn't tied to
the top level drm_device anymore. The top level drm_device is now
associated with a platform device that corresponds to MDSS wrapper
hardware.
Create mdp5_init/destroy funcs that will be used by the MDP5 driver
probe/remove. Use the HW_VERSION register in the MDP5 register address
space. Both the MDSS and MDP VERSION registers give out identical
version info.
The older mdp5_kms_init code is left as is for now, this would be removed
later when we have all the pieces to support the new device hierarchy.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
SoCs that contain MDP5 have a top level wrapper called MDSS that manages
clocks, power and irq for the sub-blocks within it.
Currently, the MDSS portions are stuffed into the MDP5 driver. This makes
it hard to represent the DT bindings in the correct way. We create a top
level MDSS helper that handles these parts. This is essentially moving out
some of the mdp5_kms irq code and MDSS register space and keeping it as a
separate entity. We haven't given any clocks to the top level MDSS yet,
but a AHB clock would be added in the future to access registers.
One thing to note is that the resources allocated by this helper are
tied to the top level platform_device (the one that allocates the
drm_device struct too). This device would be the parent to MDSS
sub-blocks like MDP5, DSI, eDP etc.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The driver gets the irq number using platform_get_irq on the main kms
platform device. This works fine since both MDP4 and MDP5 currently
have a flat device hierarchy. The platform device tied with the
drm_device points to the MDP DT node in both cases.
This won't work when MDP5 supports a tree-like hierarchy. In this
case, the platform device tied to the top level drm_device is the
MDSS DT node, and the irq we need for KMS is the one generated by
MDP5, not MDSS.
Get the irq number from the MDP4/5 kms driver itself. Each driver
can later provide the irq number based on what device hierarchy it
uses.
While we're at it, call drm_irq_install only when we have a valid KMS
driver.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
These aren't used. Probably left overs when driver was refactored to
support both MDP4 and MDP5.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Some cleanups:
- Use simpler names for DT nodes in the example
- Use references instead of dumping Document links everywhere
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The PLL in the DSI PHY block generates 2 clock outputs (Byte and Pixel
clocks) that are fed into the Multimedia Clock Controller (MMCC). The MMCC
uses these as source clocks for some of its RCGs to generate clocks that
finally feed to the DSI host controller.
Use the assigned clocks DT bindings to set up the MMCC RCGs that feed to
the DSI host. Use the DSI PHY provided clocks to set up the parents
of these assigned clocks.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The DSI node now has two ports that describe the connection between the
MDP interface output and the DSI input, and the connection between the DSI
output and the connected panel/bridge. Update the properties and the
example.
Also, use generic PHY bindings instead of the custom one.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The "qcom,data-lane-map" binding mentioned in the document is changed to
the more generic "data-lanes" property specified in:
Documentation/devicetree/bindings/media/video-interfaces.txt
The previous binding expressed physical to logical data lane mappings,
the standard "data-lanes" binding uses logical to physical data lane
mappings. Update the docs to reflect this change. The example had the
property incorrectly named as "lanes", update this too.
The MSM DSI DT bindings aren't used anywhere at the moment, so
it's okay to update this property.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
A more standard DT binding describing data lanes already exists here:
Documentation/devicetree/bindings/media/video-interfaces.txt
Use this binding instead of "qcom,data-lane-map". One difference
in the standard binding w.r.t to the existing binding is that it
provides a logical to physical mapping instead of the other way
round. Tweak the code to translate the data the way we want it.
The MSM DSI DT bindings aren't used anywhere at the moment, so
it's okay to update this property.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The DSI host links to the DSI PHY device using a custom binding. Switch to
the generic PHY bindings. The DSI PHY driver itself doesn't use the common
PHY framework for now.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The DSI interface is going to have two ports defined in its device node.
The first port is always going to be the link between the MDP output
and the input to DSI, the second port is going to be the link between
the DSI output and the connected panel/bridge:
----- ----- -------
| MDP | ------> | DSI | ------> | Panel |
----- ----- -------
(Port 0) (Port 1)
Until now, there was only one Port representing the output. Update the
DSI host driver such that it parses Port #1 for a connected device.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Address some issues wiht clock related bindings. It's okay to change these
since these bindings aren't used in any dtsi files until now.
MDP5:
- Don't ask for source clock
MDP4:
- Give a better name for MDP_TV_CLK
- Remove TV_SRC
- Add MDP_AXI_CLK
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Fix some issues with MDP4 clocks:
- mdp4_dtv_encoder tries to get "src_clk", which is a RCG(TV_SRC) in
MSM8960 and APQ8064. This isn't something the driver should access or
configure. Instead of this, configure the "mdp_clk" (MDP_TV_CLK), a
branch clock in MMCC that has the TV_SRC as its parent. Setting
rate/enabling the "mdp_clk" will eventually configure "src_clk", which
is what we want.
- Rename "mdp_clk" to "tv_clk" because that's slightly less confusing.
- Rename "mdp_axi_clk" to "bus_clk" because that's what we do elsewhere
too.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The driver expects DT to provide the parent to MDP core clock. The only
operation done to the parent clock is to set a rate. This can be
achieved by setting the rate on the core clock itsef. Don't try to
get the parent clock anymore.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The msm_iommu_map/unmap funcs have debug prints to show the list of
VA:PA mappings. Use the correct variable to print the VAs.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
The u32 type used to pass the physical addresses to iommu_map can't
accommodate 64 bit addresses. Move to dma_addr_t to ensure wrong
addresses aren't provided to the IOMMU driver.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
allowing GLSL shaders with non-unrolled loops.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCgAGBQJXiWHaAAoJELXWKTbR/J7olkkP/3buVvzBdxQmT7yMeBL2Up+F
MZ+W/pr7+gWXT/rvyY8zbEZV1txQtZDnvu8cC3h9E66TVYpTx3dYypECwiRKFt5f
HXhrkiniu65zBPhtYxloswcr686SpFOhr9rwy6cJbCCvuZQZVpQ41Fu7BinaYJc2
uGllnNmRkB7tPG/6BYQ/MAWvR7AjTaaAmcdhNZDyEHqXHiUu8NPprL0BQIwS1GMn
65pQjni/WEek6/WxncxszaDWfsLMRJPKiuPV4kAsoQDluB3ortk3k1VVNJ+n3aXw
GjlMNbU2ganEGWJS16e7HXXz3I19SQHn5mnL74X3GGL8r2x9AIZ64Zk7Ru659NBq
CW/NsSWM/TfU6T4iflbZjSVlmtbvdX5T0rDFb+lMFNXG8EvmRIc3fkbSeh6gF9sF
hc3UDS3ScQBAm8QOpDiVAsXNBGJUTsvxdDYgVUj1mjPtbD1ZDmEWYdb2fzs/n7ja
qU/CW9Ap3tModkTjaD58RoenTkbTXymhxmRd1JHoxVztkAM00fNxtGP6fTxuGLOW
snOoE9Ahdq/IzV/yZrqvWRCLTDenQ/ZxcP+fYleJ6M3qLxfHkgZX/chy/n21Q80G
Qe40uqBWreTCz6SzCEOXeaJ9RDbZfSomVfWuLzm5IGMhOmh1rqkpdgAUKQW7OvxB
e/LnruAmY/K7Yin87gK6
=Qh0U
-----END PGP SIGNATURE-----
Merge tag 'drm-vc4-next-2016-07-15' of https://github.com/anholt/linux into drm-next
This pull request brings in vc4 shader validation for branching,
allowing GLSL shaders with non-unrolled loops.
* tag 'drm-vc4-next-2016-07-15' of https://github.com/anholt/linux:
drm/vc4: Fix a "the the" typo in a comment.
drm/vc4: Fix definition of QPU_R_MS_REV_FLAGS
drm/vc4: Add a getparam to signal support for branches.
drm/vc4: Add support for branching in shader validation.
drm/vc4: Add a bitmap of branch targets during shader validation.
drm/vc4: Move validation's current/max ip into the validation struct.
drm/vc4: Add a getparam ioctl for getting the V3D identity regs.
This set of changes contains a few cleanups for existing panels as well
as improved handling of certain backlights. In addition there's support
for a few new simple panels.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJXh5uyAAoJEN0jrNd/PrOhtysQAJ1raFyTpNYltaMsiDnA117k
0rs2ILE9L6hI2p/3ibewwi1S2mVs9i9vnCBYkBNxheuspKs0SBoVVKuMUr00WvDE
fmI/rOs1Ygqh9jX8j1XIkvjtD+MHtjxmaMWymaV2F2/vpjQ3ReTLPv4cuf1odjDf
qsmRNjH+2UhxPrkp+aeVwlafcA3ZbsCJ3sqxLQVY4TMTBCZFemaKoIkQQrNahWH9
dyRwnYuQm7t2YUytIf4EoZcX14O1D4hF8NM5teFMzolSL5lACOAY+Kg0Goai9rXU
RmnGAMlCXuAWJxJm2YlJMr21TDNqsGPZHu6LpX2dNbc+K8yfNXCkiivBdS9yIx0q
qoL7BTGJupPTW2g9rXKY4fovF9gcyND2yNqyNFHAa5aq9Cw68yCV2u5Yz0oYYS8T
BlSkAuY4bpmjuL2kgpP5hNU1CZqDvjI7KKPtklGBOa3/8J4b++m/FxVZPmvquB6m
rv42bk1y5NWK3VFhLbYGmRo5mjm0BLk0/bIP3T4Uk/mbpd2aJNfJWcyMhd8waTVd
ene3iV6WYtuvZMuvaM4y94QRiH1hX+rGAaf/4tvUIBxSlKK9EBi1x6xPpVZlkJ4F
ZgYRc8E8IiWsqXAO4p9qW8ZlHGL2wCAOzZL+uu17GbURWxChC9u6vr2TEooflrgs
9OxI3YHinSbv9+Vz8yMg
=XLd7
-----END PGP SIGNATURE-----
Merge tag 'drm/panel/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/panel: Changes for v4.8-rc1
This set of changes contains a few cleanups for existing panels as well
as improved handling of certain backlights. In addition there's support
for a few new simple panels.
* tag 'drm/panel/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux:
drm/panel: simple: Add support for Starry KR122EA0SRA panel
dt-bindings: Add Starry KR122EA0SRA panel binding
dt-bindings: Add vendor prefix for Starry
dt-bindings: display: Add Sharp LQ101K1LY04 panel binding
drm/panel: simple: Add support for Sharp LQ101K1LY04
drm/panel: simple: Add support for LG LP079QX1-SP0V panel
dt-bindings: Add support for LG LP079QX1-SP0V panel
drm/panel: simple: Add support for Sharp LQ123P1JX31 panel
dt-bindings: Add Sharp LQ123P1JX31 panel binding
drm/panel: simple: Add support for Samsung LSN122DL01-C01 panel
dt-bindings: Add Samsung LSN122DL01-C01 panel binding
drm/panel: simple: Add support for LG LP097QX1-SPA1 panel
dt-bindings: Add LG LP097QX1-SPA1 panel binding
drm/panel: simple: Update backlight state property
drm/panel: simple: Remove gratuitous blank line
drm/panel: simple: Fix a couple of physical sizes
This set of changes contains a bunch of cleanups to the host1x driver as
well as the addition of a pin controller for DPAUX, which is required by
boards to configure the DPAUX pads in AUX mode (for DisplayPort) or I2C
mode (for HDMI and DDC).
Included is also a bit of rework of the SOR driver in preparation to add
DisplayPort support as well as some refactoring and cleanup.
Finally, all output drivers are converted to runtime PM, which greatly
simplifies the handling of clocks and resets.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJXh5n1AAoJEN0jrNd/PrOh+KcP/0SLO9UKvGBsfD0EFvkxx/NV
VZvqCWP0ARCGDAZn890O4sqwgHdRDF+hp0HcUt8wDt4o3VTYJIdifr/5tunOZ6+w
1IatWrjJjpyvZs9bveEvtJ8Hbkq5h0esA1StcqheRUiE0o+uQppdWO1NLO+HxssQ
f4qV4GQ7trJQdjr9OGfGJigsvOjwGVbPL7CRrKKLmbfTiqy9zhi5bOyUfojtMEL6
BvH9RMqC0ke70sGtcPgigbL7wgnbkH0uR3sV5TwU5dErrvh0tnhYU1a1ednPotJW
z56+W8hWfC3XLIiU9mju1l+3sQA0BuS9ZQ+6VhdRTKxv85CUI5dUKT0/h5BtRrK9
0XgPwrn4YpAr17oFEGdqFPhefkDkbb/1WrWmgUEi8/YaimdCXNkf8rILZvWUVQdt
q9GbbmEiGNR2FvBEN7s/nT96E5XEzfLTjOzTOP0c5RF9cOK+Ul9t0t44eBn4Wqbk
x6rTv37eieK5RVYd24xKKnzf5uSMpU+RTea4Vpr0xdH6glGcrTJ5ogub0iIsY0Jn
A9M1pKadQvu//95ZzGWEyrqAr66cDG8vGjZn9z24PRaNZEbzvY3ohj2/qOSQoRFY
HPmswshI0DnyFPWmdhhlPy3di0zNDP6kfPo6NhotoAl2Uwd+RrY/VyWjDG0dwV0R
nSkcnGES5hnf3gguXEmO
=7xlG
-----END PGP SIGNATURE-----
Merge tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v4.8-rc1
This set of changes contains a bunch of cleanups to the host1x driver as
well as the addition of a pin controller for DPAUX, which is required by
boards to configure the DPAUX pads in AUX mode (for DisplayPort) or I2C
mode (for HDMI and DDC).
Included is also a bit of rework of the SOR driver in preparation to add
DisplayPort support as well as some refactoring and cleanup.
Finally, all output drivers are converted to runtime PM, which greatly
simplifies the handling of clocks and resets.
* tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux: (35 commits)
drm/tegra: sor: Reject HDMI 2.0 modes
drm/tegra: sor: Prepare for generic PM domain support
drm/tegra: dsi: Prepare for generic PM domain support
drm/tegra: sor: Make XBAR configurable per SoC
drm/tegra: sor: Use sor1_src clock to set parent for HDMI
dt-bindings: display: tegra: Add source clock for SOR
drm/tegra: sor: Implement sor1_brick clock
drm/tegra: sor: Implement runtime PM
drm/tegra: hdmi: Implement runtime PM
drm/tegra: dsi: Implement runtime PM
drm/tegra: dc: Implement runtime PM
drm/tegra: hdmi: Enable audio over HDMI
drm/tegra: sor: Do not support deep color modes
drm/tegra: sor: Extract tegra_sor_mode_set()
drm/tegra: sor: Split out tegra_sor_apply_config()
drm/tegra: sor: Rename tegra_sor_calc_config()
drm/tegra: sor: Factor out tegra_sor_set_parent_clock()
drm/tegra: dpaux: Add pinctrl support
dt-bindings: Add bindings for Tegra DPAUX pinctrl driver
drm/tegra: Prepare DPAUX for supporting generic PM domains
...
Please consider merging this tag, which contains the v4 misc fixes and add RK3399 eDP support patches[0] I sent on 2016-06-29, rebased onto v4.7-rc5.
* 'upstream/analogix-dp-20160705' of git://github.com/yakir-Yang/linux:
dt-bindings: analogix_dp: rockchip: correct the wrong compatible name
drm/rockchip: analogix_dp: introduce the pclk for grf
drm/bridge: analogix_dp: fix no drm hpd event when panel plug in
drm/rockchip: analogix_dp: update the comments about why need to hardcode VOP output mode
drm/rockchip: analogix_dp: correct the connector display color format and bpc
drm/bridge: analogix_dp: passing the connector as an argument in .get_modes()
drm/rockchip: analogix_dp: make panel detect to an optional action
drm/rockchip: analogix_dp: add rk3399 eDP support
drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting
drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1
drm/rockchip: analogix_dp: split the lcdc select setting into device data
- atomic mode setting conversion
- replace DMFC FIFO allocation mechanism with a fixed allocation
that is good enough for all cases
- support for external bridges connected to parallel-display
- improved error handling in imx-ldb, imx-tve, and parallel-display
- some code cleanup in imx-tve
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJXh1raAAoJEFDCiBxwnmDrWDIQALgkGU+38W6zspoNI1n317wy
QiPk/B7j56Um2w/qw8IgAm+pXcps3g1cGVc0zXlXsF2Kft7FmbNPll5qTFrgXc+c
odP2aOx4znFOPmMYuODKHL4GEG7F7qk1f/cVs4APZf0dupLEcxYsUHnTN/Z90hd7
JmPdbXMsC0ay/ZAvbtPTpf7BDkeUUF6vCM1JriJ0ngBlIq4LOocQOZGdA66zAnJM
fxVxQ/HRGEIIn8YMwk+Rbbj6iVTl0quOcXchILtBB6JK0OR3J0HUKDOS1hzLI29E
Y0kgZSDzQcE1U2BcHTtIlpa9hWqySVhv6tRFx2FVivy+H3wa2sQZ+rvpQKV6jNlx
0gme4b1GkX76oxhtg5nwj+Vhxazo1ANj+ezXJclr2FT2P3flGnzlBK9xQN68jOGy
cJEGKcFrO7BbgF22UP3MKCHl6A74NuutFQ/SR9ZetspFtEmzmUeae8shhJw0FVUr
ent5IeWeeZBC4KmtgIBtBwKM3PB/O7vmFVJGP47Y3uMR5qhzxUBQKTnoBIuFkgjz
3K1kDqR0AimDq+M9n8nnHXihYffFNtb4gBzbTaZTZUxYfsz8Uoe/kBpe2Gc8dcxq
KYTCbJFZ49H7on5/wDD3P98m7rEnvWAcP3k/ZzS2tBhNTAaQprkq+tQL7+JFpXcV
qTgSznrXDVlpgVXm4PnI
=lWas
-----END PGP SIGNATURE-----
Merge tag 'imx-drm-next-2016-07-14' of git://git.pengutronix.de/git/pza/linux into drm-next
imx-drm updates
- atomic mode setting conversion
- replace DMFC FIFO allocation mechanism with a fixed allocation
that is good enough for all cases
- support for external bridges connected to parallel-display
- improved error handling in imx-ldb, imx-tve, and parallel-display
- some code cleanup in imx-tve
* tag 'imx-drm-next-2016-07-14' of git://git.pengutronix.de/git/pza/linux:
drm/imx: parallel-display: add bridge support
drm/imx: parallel-display: check return code from of_get_drm_display_mode()
gpu: ipu-v3: ipu-dc: don't bug out on invalid bus_format
drm/imx: imx-tve: fix the error message
drm/imx: imx-tve: remove unneeded 'or' operation
drm/imx: imx-tve: check the value returned by regulator_set_voltage()
drm/imx: imx-ldb: check return code on panel attach
drm/imx: turn remaining container_of macros into inline functions
drm/imx: store internal bus configuration in crtc state
drm/imx: remove empty mode_set encoder callbacks
drm/imx: atomic phase 3 step 3: Advertise DRIVER_ATOMIC
drm/imx: atomic phase 3 step 2: Legacy callback fixups
drm/bridge: dw-hdmi: Remove the legacy drm_connector_funcs structure
drm/imx: atomic phase 3 step 1: Use atomic configuration
drm/imx: Remove encoders' ->prepare callbacks
drm/imx: atomic phase 2 step 2: Track plane_state->fb correctly in ->page_flip
drm/imx: atomic phase 2 step 1: Wire up state ->reset, ->duplicate and ->destroy
drm/imx: atomic phase 1: Use transitional atomic CRTC and plane helpers
gpu: ipu-v3: ipu-dmfc: Use static DMFC FIFO allocation mechanism
drm/imx: ipuv3 plane: Check different types of plane separately
The current output code only supports connection to drm panels.
Add code to support drm bridge, to support connections to
external connectors.
Signed-off-by: Meng Yi <meng.yi@nxp.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
This patch rework the output code to add of_graph dt binding support
for panel device and also keeps the backward compatibility
Signed-off-by: Meng Yi <meng.yi@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stefan Agner <stefan@agner.ch>
of_node_put needs to be called when the device node which is got
from of_parse_phandle has finished using, but current code only
calls it at error path, fix it by adding it at correct code path.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
One regression in the Device Tree handling for OMAP NAND handling of the ELM
node. TI migrated to using the property name "ti,elm-id", but forgot to keep
compatibility with the old "elm_id" property.
Also, might as well send out this MAINTAINERS fixup now.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXiYHwAAoJEFySrpd9RFgtJK0P/0xH8ChIrWio8zakcndyjIb+
LdHXlkrQfXs/6vzVAaZLeVI/KnElUL4jIVr2Xg4QYYLdyg/VzOyOGMpb2hdNvYZo
RSJf2wI+k0vcP68CQFROl+Sj2FOpWjDRB92zxyikk1D++O6jOLQWK4oUBhNgximG
qmPBl7mzhjAPrFOu1DJVIcaXxC2t5JQffAUCy0rrGBmhfiZgKxlwDnS7raumj6eq
8xBil5UoFDfIWqneh5kKphexm3t0gSdibi4V2W6EKvRK2WAhcunfBLEld7qo0Zy1
lgdaoLgEsgqjA58oQ/4MdVMZDPfin4JlKsdUcWRVXpGl5nxIB6iAJzyTHPHgltL3
aLJFjP0oT9emUI4T4cAzWRYa9M2RKOIjwfNrrjWYjkb3NOa4OIg+9xWgy8CkkeJG
BTGndVCBjXLZ1k6enQUKZ8Wf+c8BRZlVFTsvxFx89VOie3+NwfUK6Cv6mOXUdCk8
TyxYF/8R2fazP46fSCv9tW2A0FakHsNqqVm9kUDEV+c/juLtzJCHTwwRUjFJxopv
2oyHqeAUjNx65usp+vTw96oHp3BXef8Cw/9PIck3R6E6LVaZuXKlMBADP6/DLYmS
XoufM25SuPg6d0WcSzcaket60tP8wNPhsn4MB0W0rHGnMaoKY4svbew0IGSIwJPt
uWaPMn/FOVWTxcID1ln1
=tSga
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20160715' of git://git.infradead.org/linux-mtd
Pull MTD fix from Brian Norris:
"Late MTD fix for v4.7:
One regression in the Device Tree handling for OMAP NAND handling of
the ELM node. TI migrated to using the property name "ti,elm-id", but
forgot to keep compatibility with the old "elm_id" property.
Also, might as well send out this MAINTAINERS fixup now"
* tag 'for-linus-20160715' of git://git.infradead.org/linux-mtd:
mtd: nand: omap2: Add check for old elm binding
MAINTAINERS: Add file patterns for mtd device tree bindings
Nothing is decrementing the index "i" while we are cleaning up the
fragments we could not successful transmit.
Fixes: 9cde94506e ("bgmac: implement scatter/gather support")
Reported-by: coverity (CID 1352048)
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
We don't use it in shader validation currently, so it had no effect,
but best to fix it anyway in case we do some day.
Signed-off-by: Eric Anholt <eric@anholt.net>
Userspace needs to know if it can create shaders that do branching.
Otherwise, for backwards compatibility with old kernels it needs to
lower if statements to conditional assignments.
Signed-off-by: Eric Anholt <eric@anholt.net>
We're already checking that branch instructions are between the start
of the shader and the proper PROG_END sequence. The other thing we
need to make branching safe is to verify that the shader doesn't read
past the end of the uniforms stream.
To do that, we require that at any basic block reading uniforms have
the following instructions:
load_imm temp, <next offset within uniform stream>
add unif_addr, temp, unif
The instructions are generated by userspace, and the kernel verifies
that the load_imm is of the expected offset, and that the add adds it
to a uniform. We track which uniform in the stream that is, and at
draw call time fix up the uniform stream to have the address of the
start of the shader's uniforms at that location.
Signed-off-by: Eric Anholt <eric@anholt.net>
This isn't used yet, it's just a first step toward loop validation.
During the main parsing of instructions, we need to know when we hit a
new basic block so that we can reset validated state.
v2: Fix a stray semicolon after an if block. (caught by kbuild test).
Signed-off-by: Eric Anholt <eric@anholt.net>
Pull input fixes from Dmitry Torokhov:
"A few last-minute updates for the input subsystem"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input:
Input: ts4800-ts - add missing of_node_put after calling of_parse_phandle
Input: synaptics-rmi4 - use of_get_child_by_name() to fix refcount
Revert "Input: wacom_w8001 - drop use of ABS_MT_TOOL_TYPE"
Input: xpad - validate USB endpoint count during probe
Input: add SW_PEN_INSERTED define
Jiri Pirko says:
====================
mlxsw: Couple of fixes
Couple of fixes for mlxsw driver from Ido.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Packets entering the switch are mapped to a Switch Priority (SP)
according to their PCP value (untagged frames are mapped to SP 0).
The packets are classified to a priority group (PG) buffer in the port's
headroom according to their SP.
The switch maintains another mapping (SP to IEEE priority), which is
used to generate PFC frames for lossless PGs. This mapping is
initialized to IEEE = SP % 8.
Therefore, when mapping SP 'x' to PG 'y' we create a situation in which
an IEEE priority is mapped to two different PGs:
IEEE 'x' ---> SP 'x' ---> PG 'y'
IEEE 'x' ---> SP 'x + 8' ---> PG '0' (default)
Which is invalid, as a flow can use only one PG buffer.
Fix this by mapping both SP 'x' and 'x + 8' to the same PG buffer.
Fixes: 8e8dfe9fdf ("mlxsw: spectrum: Add IEEE 802.1Qaz ETS support")
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The number of supported traffic classes that can have ETS and PFC
simultaneously enabled is not subject to user configuration, so make
sure we always initialize them to the correct values following a set
operation.
Fixes: 8e8dfe9fdf ("mlxsw: spectrum: Add IEEE 802.1Qaz ETS support")
Fixes: d81a6bdb87 ("mlxsw: spectrum: Add IEEE 802.1Qbb PFC support")
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
We can't have PAUSE frames and PFC both enabled on the same port, but
the fact that ieee_setpfc() was called doesn't necessarily mean PFC is
enabled.
Only emit errors when PAUSE frames and PFC are enabled simultaneously.
Fixes: d81a6bdb87 ("mlxsw: spectrum: Add IEEE 802.1Qbb PFC support")
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The device supports link autonegotiation, so let the user know about it
by indicating support via ethtool ops.
Fixes: 56ade8fe3f ("mlxsw: spectrum: Add initial support for Spectrum ASIC")
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
When setting a new speed we need to disable and enable the port for the
changes to take effect. We currently only do that if the operational
state of the port is up. However, setting a new speed following link
training failure will require us to explicitly set the port down and then
up.
Instead, disable and enable the port based on its administrative state.
Fixes: 56ade8fe3f ("mlxsw: spectrum: Add initial support for Spectrum ASIC")
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Pull workqueue fix from Tejun Heo:
"The optimization for setting unbound worker affinity masks collided
with recent scheduler changes triggering warning messages.
This late pull request fixes the bug by removing the optimization"
* 'for-4.7-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq:
workqueue: Fix setting affinity of unbound worker threads
Without this check, the following XFS_I invocations would return bad
pointers when used on non-XFS inodes (perhaps pointers into preceding
allocator chunks).
This could be used by an attacker to trick xfs_swap_extents into
performing locking operations on attacker-chosen structures in kernel
memory, potentially leading to code execution in the kernel. (I have
not investigated how likely this is to be usable for an attack in
practice.)
Signed-off-by: Jann Horn <jann@thejh.net>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Dave Chinner <david@fromorbit.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Jeff Kirsher says:
====================
Intel Wired LAN Driver Updates 2016-07-14
This series contains fixes to i40e and ixgbe.
Alex fixes issues found in i40e_rx_checksum() which was broken, where the
checksum was being returned valid when it was not.
Kiran fixes a bug which was found when we abruptly remove a cable which
caused a panic. Set the VSI broadcast promiscuous mode during VSI add
sequence and prevents adding MAC filter if specified MAC address is
broadcast.
Paolo Abeni fixes a bug by returning the actual work done, capped to
weight - 1, since the core doesn't allow to return the full budget when
the driver modifies the NAPI status.
Guilherme Piccoli fixes an issue where the q_vector initialization
routine sets the affinity _mask of a q_vector based on v_idx value.
This means a loop iterates on v_idx, which is an incremental value, and
the cpumask is created based on this value. This is a problem in
systems with multiple logical CPUs per core (like in SMT scenarios).
Changed the way q_vector's affinity_mask is created to resolve the issue.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
ethtool -i provides a driver version that is hard coded.
Export the same value via "modinfo".
Signed-off-by: Grant Grundler <grundler@chromium.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
The per-socket rate limit for 'challenge acks' was introduced in the
context of limiting ack loops:
commit f2b2c582e8 ("tcp: mitigate ACK loops for connections as tcp_sock")
And I think it can be extended to rate limit all 'challenge acks' on a
per-socket basis.
Since we have the global tcp_challenge_ack_limit, this patch allows for
tcp_challenge_ack_limit to be set to a large value and effectively rely on
the per-socket limit, or set tcp_challenge_ack_limit to a lower value and
still prevents a single connections from consuming the entire challenge ack
quota.
It further moves in the direction of eliminating the global limit at some
point, as Eric Dumazet has suggested. This a follow-up to:
Subject: tcp: make challenge acks less predictable
Cc: Eric Dumazet <edumazet@google.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Neal Cardwell <ncardwell@google.com>
Cc: Yuchung Cheng <ycheng@google.com>
Cc: Yue Cao <ycao009@ucr.edu>
Signed-off-by: Jason Baron <jbaron@akamai.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Fix a memory leak on probe error of the airspy usb device driver.
The problem is triggered when more than 64 usb devices register with
v4l2 of type VFL_TYPE_SDR or VFL_TYPE_SUBDEV.
The memory leak is caused by the probe function of the airspy driver
mishandeling errors and not freeing the corresponding control structures
when an error occours registering the device to v4l2 core.
A badusb device can emulate 64 of these devices, and then through
continual emulated connect/disconnect of the 65th device, cause the
kernel to run out of RAM and crash the kernel, thus causing a local DOS
vulnerability.
Fixes CVE-2016-5400
Signed-off-by: James Patrick-Evans <james@jmp-e.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
Cc: stable@vger.kernel.org # 3.17+
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
In commit 2c1ea4c700 ("EDAC, sb_edac: Use cpu family/model in driver
detection") I broke Knights Landing because I failed to notice that it
called a wrapper macro "sbridge_get_all_devices_knl" instead of
"sbridge_get_all_devices" like all the other types.
Now that we include the processor type in the pci_id_table structure we
can skip the wrappers and just have the sbridge_get_all_devices() check
the type to decide whether to allow duplicate devices and controllers to
have registers spread across buses.
Fixes: 2c1ea4c700 ("EDAC, sb_edac: Use cpu family/model in driver detection")
Tested-by: Lukasz Odzioba <lukasz.odzioba@intel.com>
Acked-by: Aristeu Rozanski <aris@redhat.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
