Chun-Jie Chen
a677bdf8b6
clk: mediatek: Add MT8186 ipesys clock support
...
Add MT8186 ipesys clock controller which provides clock gate
control for Image Process Engine.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-16-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:41 -07:00
Chun-Jie Chen
8c3adc5d2e
clk: mediatek: Add MT8186 mdpsys clock support
...
Add MT8186 mdpsys clock controller which provides clock gate
control in Multimedia Data Path.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-15-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:40 -07:00
Chun-Jie Chen
6f2e120824
clk: mediatek: Add MT8186 camsys clock support
...
Add MT8186 camsys clock controllers which provide clock gate
control for camera IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-14-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:40 -07:00
Chun-Jie Chen
fc21950283
clk: mediatek: Add MT8186 vencsys clock support
...
Add MT8186 vencsys clock controller which provide clock gate
control for video encoder.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-13-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:40 -07:00
Chun-Jie Chen
7e23620dff
clk: mediatek: Add MT8186 vdecsys clock support
...
Add MT8186 vdec clock controller which provide clock gate
control for video decoder.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-12-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:40 -07:00
Chun-Jie Chen
a6c0c9b8fc
clk: mediatek: Add MT8186 imgsys clock support
...
Add MT8186 imgsys clock controllers which provide clock gate
control for image IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-11-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:40 -07:00
Chun-Jie Chen
b6da76d6eb
clk: mediatek: Add MT8186 wpesys clock support
...
Add MT8186 wpesys clock controllers which provide clock gate
control in Wrapping Engine.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-10-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:40 -07:00
Chun-Jie Chen
c8c36b996f
clk: mediatek: Add MT8186 mmsys clock support
...
Add MT8186 mmsys clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start mmsys clock driver.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-9-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:40 -07:00
Chun-Jie Chen
e4a424461c
clk: mediatek: Add MT8186 mfgsys clock support
...
Add MT8186 mfg clock controller which provides clock gate
control for GPU.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-8-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:39 -07:00
Chun-Jie Chen
66cd0b4b0c
clk: mediatek: Add MT8186 imp i2c wrapper clock support
...
Add MT8186 imp i2c wrapper clock controllers which provide clock gate
control in i2c IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-7-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:39 -07:00
Chun-Jie Chen
97f0cc59e5
clk: mediatek: Add MT8186 apmixedsys clock support
...
Add MT8186 apmixedsys clock controller which provides Plls
generated from SoC.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-6-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:39 -07:00
Chun-Jie Chen
4d6534ec55
clk: mediatek: Add MT8186 infrastructure clock support
...
Add MT8186 infrastructure clock controller which provides
clock gate control for basic IP like pwm, uart, spi and so on.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-5-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:39 -07:00
Chun-Jie Chen
c19df9619e
clk: mediatek: Add MT8186 topckgen clock support
...
Add MT8186 topckgen clock controller which provides muxes, dividers
to handle variety clock selection in other IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-4-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:39 -07:00
Chun-Jie Chen
1f2967a17c
clk: mediatek: Add MT8186 mcusys clock support
...
Add MT8186 mcusys clock controller which provides muxes
to select the clock source of APMCU.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-3-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:39 -07:00
Sam Shih
ec97d23c8e
clk: mediatek: add mt7986 clock support
...
Add MT7986 clock support, include topckgen, apmixedsys,
infracfg, and ethernet subsystem clocks.
Signed-off-by: Sam Shih <sam.shih@mediatek.com >
Link: https://lore.kernel.org/r/20211217121148.6753-4-sam.shih@mediatek.com
Reviewed-by: Ryder Lee <ryder.lee@kernel.org >
[sboyd@kernel.org: Fix typos in Kconfig, there are more existing typos
from where they were copied from of but whatever]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-06 18:37:55 -08:00
Chun-Jie Chen
74e1652ce9
clk: mediatek: Add MT8195 apusys clock support
...
Add MT8195 apusys clock controller which provides PLLs
in AI processor Unit.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20210914021633.26377-25-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:39 -07:00
Chun-Jie Chen
222e0fbcef
clk: mediatek: Add MT8195 imp i2c wrapper clock support
...
Add MT8195 imp i2c wrapper clock controllers which provide clock gate
control in I2C IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20210914021633.26377-24-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:39 -07:00
Chun-Jie Chen
993e9a77e2
clk: mediatek: Add MT8195 wpesys clock support
...
Add MT8195 wpesys clock controllers which provide clock gate
control in Wrapping Engine.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210914021633.26377-23-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:39 -07:00
Chun-Jie Chen
50df772268
clk: mediatek: Add MT8195 vppsys1 clock support
...
Add MT8195 vppsys1 clock controller which provides clock gate
controller for Video Processor Pipe.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20210914021633.26377-22-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:39 -07:00
Chun-Jie Chen
f5bf0c1b48
clk: mediatek: Add MT8195 vppsys0 clock support
...
Add MT8195 vppsys0 clock controller which provides clock gate
controller for Video Processor Pipe.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20210914021633.26377-21-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:39 -07:00
Chun-Jie Chen
b5d728d8f1
clk: mediatek: Add MT8195 vencsys clock support
...
Add MT8195 vencsys clock controllers which provide clock gate
control for video encoder.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210914021633.26377-20-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:39 -07:00
Chun-Jie Chen
269987505b
clk: mediatek: Add MT8195 vdosys1 clock support
...
Add MT8195 vdosys1 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210914021633.26377-19-chun-jie.chen@mediatek.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:38 -07:00
Chun-Jie Chen
70282c90d4
clk: mediatek: Add MT8195 vdosys0 clock support
...
Add MT8195 vdosys0 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210914021633.26377-18-chun-jie.chen@mediatek.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:38 -07:00
Chun-Jie Chen
d7338d06ac
clk: mediatek: Add MT8195 vdecsys clock support
...
Add MT8195 vdec clock controllers which provide clock gate
control for video decoder.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20210914021633.26377-17-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:38 -07:00
Chun-Jie Chen
24da2c2429
clk: mediatek: Add MT8195 scp adsp clock support
...
Add MT8195 scp adsp clock controller which provides clock gate
control for Audio DSP.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20210914021633.26377-16-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:38 -07:00
Chun-Jie Chen
35016f10c0
clk: mediatek: Add MT8195 mfgcfg clock support
...
Add MT8195 mfg clock controller which provides clock gate
control for GPU.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210914021633.26377-15-chun-jie.chen@mediatek.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:38 -07:00
Chun-Jie Chen
d9943b6d71
clk: mediatek: Add MT8195 ipesys clock support
...
Add MT8195 ipesys clock controller which provides clock gate
control for Image Process Engine.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210914021633.26377-14-chun-jie.chen@mediatek.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:38 -07:00
Chun-Jie Chen
9c4fec14ae
clk: mediatek: Add MT8195 imgsys clock support
...
Add MT8195 imgsys clock controllers which provide clock gate
control for image IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20210914021633.26377-13-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:38 -07:00
Chun-Jie Chen
7b2e1de8ae
clk: mediatek: Add MT8195 ccusys clock support
...
Add MT8195 ccusys clock controller which provides clock gate
control in Camera Computing Unit.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20210914021633.26377-12-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:38 -07:00
Chun-Jie Chen
9d0c6572d5
clk: mediatek: Add MT8195 camsys clock support
...
Add MT8195 camsys clock controllers which provide clock gate
control for camera IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20210914021633.26377-11-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:37 -07:00
Chun-Jie Chen
e2edf59dec
clk: mediatek: Add MT8195 infrastructure clock support
...
Add MT8195 infrastructure clock controller which provides
clock gate control for basic IP like pwm, uart, spi and so on.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210914021633.26377-10-chun-jie.chen@mediatek.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:37 -07:00
Chun-Jie Chen
a2a2c5fc5c
clk: mediatek: Add MT8195 peripheral clock support
...
Add MT8195 peripheral clock controller which provides clock
gate control for ethernet/flashif/pcie/ssusb.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20210914021633.26377-9-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:37 -07:00
Chun-Jie Chen
0360be014c
clk: mediatek: Add MT8195 topckgen clock support
...
Add MT8195 topckgen clock controller which provides muxes, dividers
to handle variety clock selection in other IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210914021633.26377-8-chun-jie.chen@mediatek.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:37 -07:00
Chun-Jie Chen
3e9121f16c
clk: mediatek: Add MT8195 apmixedsys clock support
...
Add MT8195 apmixedsys clock controller which provides Plls
generated from SoC 26m and ssusb clock gate control.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20210914021633.26377-7-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 15:05:37 -07:00
Chun-Jie Chen
441decf91e
clk: mediatek: Add MT8192 vencsys clock support
...
Add MT8192 vencsys clock provider
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com >
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210726105719.15793-22-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-07-27 10:53:10 -07:00
Chun-Jie Chen
25f3d97e39
clk: mediatek: Add MT8192 vdecsys clock support
...
Add MT8192 vdecsys and vdecsys soc clock providers
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com >
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210726105719.15793-21-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-07-27 10:53:10 -07:00
Chun-Jie Chen
aff125adc0
clk: mediatek: Add MT8192 scp adsp clock support
...
Add MT8192 scp adsp clock provider
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com >
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210726105719.15793-20-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-07-27 10:53:10 -07:00
Chun-Jie Chen
a1a5b6b0a8
clk: mediatek: Add MT8192 msdc clock support
...
Add MT8192 msdc and msdc top clock providers
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com >
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210726105719.15793-19-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-07-27 10:53:09 -07:00
Chun-Jie Chen
9d44859bfe
clk: mediatek: Add MT8192 mmsys clock support
...
Add MT8192 mmsys clock provider
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com >
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com >
Link: https://lore.kernel.org/r/20210726105719.15793-18-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-07-27 10:53:09 -07:00
Chun-Jie Chen
34e1b85549
clk: mediatek: Add MT8192 mfgcfg clock support
...
Add MT8192 mfgcfg clock provider
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com >
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210726105719.15793-17-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-07-27 10:53:09 -07:00
Chun-Jie Chen
b565d41f8c
clk: mediatek: Add MT8192 mdpsys clock support
...
Add MT8192 mdpsys clock provider
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com >
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210726105719.15793-16-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-07-27 10:53:09 -07:00
Chun-Jie Chen
7f621d25d9
clk: mediatek: Add MT8192 ipesys clock support
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Add MT8192 ipesys clock provider
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com >
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210726105719.15793-15-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-07-27 10:53:08 -07:00
Chun-Jie Chen
71193c46bd
clk: mediatek: Add MT8192 imp i2c wrapper clock support
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Add MT8192 imp i2c wrapper clock provider
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com >
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210726105719.15793-14-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-07-27 10:53:08 -07:00
Chun-Jie Chen
014a4881a2
clk: mediatek: Add MT8192 imgsys clock support
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Add MT8192 imgsys and imgsys2 clock providers
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com >
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210726105719.15793-13-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-07-27 10:53:08 -07:00
Chun-Jie Chen
cebef18833
clk: mediatek: Add MT8192 camsys clock support
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Add MT8192 camsys and camsys raw clock providers
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com >
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210726105719.15793-12-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-07-27 10:53:07 -07:00
Chun-Jie Chen
f61e83488d
clk: mediatek: Add MT8192 audio clock support
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Add MT8192 audio clock provider
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com >
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210726105719.15793-11-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-07-27 10:53:07 -07:00
Chun-Jie Chen
710573dee3
clk: mediatek: Add MT8192 basic clocks support
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Add MT8192 basic clock providers, include topckgen, apmixedsys,
infracfg and pericfg.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com >
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210726105719.15793-10-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-07-27 10:53:07 -07:00
Fabien Parent
a682248321
clk: mediatek: Add MT8167 clock support
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Add the following clock support for MT8167 SoC: topckgen, apmixedsys,
infracfg, audsys, imgsys, mfgcfg, vdecsys.
Signed-off-by: Fabien Parent <fparent@baylibre.com >
Link: https://lore.kernel.org/r/20200918132303.2831815-2-fparent@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-10-13 15:46:01 -07:00
Linus Torvalds
6f630784cc
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
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Pull clk updates from Stephen Boyd:
"This time around we have four lines of diff in the core framework,
removing a function that isn't used anymore. Otherwise the main new
thing for the common clk framework is that it is selectable in the
Kconfig language now. Hopefully this will let clk drivers and clk
consumers be testable on more than the architectures that support the
clk framework. The goal is to introduce some Kunit tests for the
framework.
Outside of the core framework we have the usual set of various driver
updates and non-critical fixes. The dirstat shows that the new
Baikal-T1 driver is the largest addition this time around in terms of
lines of code. After that the x86 (Intel), Qualcomm, and Mediatek
drivers introduce many lines to support new or upcoming SoCs. After
that the dirstat shows the usual suspects working on their SoC support
by fixing minor bugs, correcting data and converting some of their DT
bindings to YAML.
Core:
- Allow the COMMON_CLK config to be selectable
New Drivers:
- Clk driver for Baikal-T1 SoCs
- Mediatek MT6765 clock support
- Support for Intel Agilex clks
- Add support for X1830 and X1000 Ingenic SoC clk controllers
- Add support for the new Renesas RZ/G1H (R8A7742) SoC
- Add support for Qualcomm's MSM8939 Generic Clock Controller
Updates:
- Support IDT VersaClock 5P49V5925
- Bunch of updates for HSDK clock generation unit (CGU) driver
- Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
- Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
- Enable supply regulators for GPU gdscs on Qualcomm SoCs
- Add support for Si5342, Si5344 and Si5345 chips
- Support custom flags in Xilinx zynq firmware
- Various small fixes to the Xilinx clk driver
- A single minor rounding fix for the legacy Allwinner clock support
- A few patches from Abel Vesa as preparation of adding audiomix
clock support on i.MX
- A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and
clk-pllv3 drivers
- Drop dependency on ARM64 for i.MX8M clock driver, to support
aarch32 mode on aarch64 hardware
- A series from Peng Fan to improve i.MX8M clock drivers, using
composite clock for core and bus clk slice
- Set a better parent clock for flexcan on i.MX6UL to support CiA102
defined bit rates
- A couple changes for EMC frequency scaling on Tegra210
- Support for CPU frequency scaling on Tegra20/Tegra30
- New clk gate for CSI test pattern generator on Tegra210
- Regression fixes for Samsung exynos542x and exynos5433 SoCs
- Use of fallthrough; attribute for Samsung s3c24xx
- Updates and fixup HDMI and video clocks on Meson8b
- Fixup reset polarity on Meson8b
- Fix GPU glitch free mux switch on Meson gx and g12
- A minor fix for the currently unused suspend/resume handling on
Renesas RZ/A1 and RZ/A2
- Two more conversions of Renesas DT bindings to json-schema
- Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (155 commits)
clk: mediatek: Remove ifr{0,1}_cfg_regs structures
clk: baikal-t1: remove redundant assignment to variable 'divider'
clk: baikal-t1: fix spelling mistake "Uncompatible" -> "Incompatible"
dt-bindings: clock: Add a missing include to MMP Audio Clock binding
dt: Add bindings for IDT VersaClock 5P49V5925
clk: vc5: Add support for IDT VersaClock 5P49V6965
clk: Add Baikal-T1 CCU Dividers driver
clk: Add Baikal-T1 CCU PLLs driver
dt-bindings: clk: Add Baikal-T1 CCU Dividers binding
dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
clk: mediatek: assign the initial value to clk_init_data of mtk_mux
clk: mediatek: Add MT6765 clock support
clk: mediatek: add mt6765 clock IDs
dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC
dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC
dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC
CLK: HSDK: CGU: add support for 148.5MHz clock
CLK: HSDK: CGU: support PLL bypassing
CLK: HSDK: CGU: check if PLL is bypassed first
clk: clk-si5341: Add support for the Si5345 series
...
2020-06-10 11:42:19 -07:00
Owen Chen
1aca9939bf
clk: mediatek: Add MT6765 clock support
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Add MT6765 clock support, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.
Signed-off-by: Owen Chen <owen.chen@mediatek.com >
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com >
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com >
Link: https://lore.kernel.org/r/1582278742-1626-6-git-send-email-macpaul.lin@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-05-28 21:23:18 -07:00
