Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift
value of 4) instead of the currently configured 32 bytes L1-cache line
size.
Reported-by: Daniel Gonzalez <dgcbueu@gmail.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
All platforms that require a special MIPS_L1_CACHE_SHIFT value have been
updated, such that we can now make MIPS_L1_CACHE_SHIFT default to the
appropriate integer value based on the select MIPS_L1_CACHE_SHIFT_<N>
variable.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
In order to avoid keeping an ever growing list of chips which need to
select a specific MIPS_L1_CACHE_SHIFT value introduce multiple internal
and non-exposed Kconfig symbols for the various MIPS_L1_CACHE_SHIFT
values out there and update the relevant Kconfig symbols to select them.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
This fixes the following sparse warnings:
arch/mips/bcm47xx/board.c:39:16: warning: Using plain integer as NULL pointer
arch/mips/bcm47xx/board.c:46:16: warning: Using plain integer as NULL pointer
arch/mips/bcm47xx/board.c:53:16: warning: Using plain integer as NULL pointer
arch/mips/bcm47xx/board.c:78:16: warning: Using plain integer as NULL pointer
arch/mips/bcm47xx/board.c:99:16: warning: Using plain integer as NULL pointer
arch/mips/bcm47xx/board.c:109:16: warning: Using plain integer as NULL pointer
arch/mips/bcm47xx/board.c:124:16: warning: Using plain integer as NULL pointer
arch/mips/bcm47xx/board.c:155:16: warning: Using plain integer as NULL pointer
arch/mips/bcm47xx/board.c:177:16: warning: Using plain integer as NULL pointer
arch/mips/bcm47xx/board.c:189:16: warning: Using plain integer as NULL pointer
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6318/
With this patch we prevent the irq from being fired when it is
registered. The Hardware fires an IRQ when input signal XOR polarity
AND gpio mask is 1. Now we are setting polarity to a vlaue so that is
is 0 when we register it.
In addition we also set the irq mask register to 0 when the irq handler
is initialized, so all gpio irqs are masked and there will be no
unexpected irq.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Tested-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6304/
BUG() can be a noop if CONFIG_BUG is not selected,
leading to the following build problem on a randconfig:
arch/mips/bcm63xx/cpu.c: In function 'detect_cpu_clock':
arch/mips/bcm63xx/cpu.c:254:1: error: control reaches end of
non-void function [-Werror=return-type]
We fix this problem by replacing BUG() with panic() since it's
best to handle the case of an unknown board instead of silently
returning a random clock frequency.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Acked-by: Steven J. Hill <Steven.Hill@imgtec.com>
Acked-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5932/
This old wgt634u.c was trying to implement a bit ugly support for
Netgear WGT634U. It provided info about LED, flash mapping & layout and
was trying to handle reset button.
This is not needed anymore as we have replacement for all this stuff.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6302/
So far this adds support for one Netgear model only, but it's designed
and ready to add many more device. We could hopefully import database
from OpenWrt.
Support for SSB is currently disabled, because SSB doesn't implement IRQ
domain yet.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6300/
So far this is mostly just a proof of concept, database consists of a
single device. Creating a nice iterateable array wasn't an option
because devices have different amount of LEDs. And we don't want to
waste memory just because of support for a device with dozens on LEDs.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6299/
The BCM4706 has a problem with the CPU wait instruction. When r4k_wait
or r4k_wait_irqoff is used will just hang and not return from a
msleep(). Removing the cpu_wait functionality is a workaround for this
problem. The BCM4716 does not have this problem.
The BCM4706 SoC uses a MIPS 74K V4.9 CPU.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6288/
The early serial code is not needed because we already have early
printk support provided by common/earlycons.c
This change also fixes the following build error that occurs when
CONFIG_SERIAL_8250 is not configured for Netlogic XLR boards:
arch/mips/built-in.o: In function `nlm_early_serial_setup':
setup.c:(.init.text+0x274): undefined reference to `early_serial_setup'
make: *** [vmlinux] Error 1
Reported-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6083/
Add the SYS block registers for XLP9XX, most of them have changed.
The wakeup sequence has been updated to set the coherent mode from
the main thread rather than the woken up thread.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6280/
Most IO block offsets have changed in XLP9XX. Update iomap.h to add the
new addresses of different SoC blocks like PIC, SYS, UART etc. that are
needed by the base code.
On XLP9xx, the SoC blocks of other nodes are seen on a PCI bus
corresponding to the node. Update iomap code to reflect this.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6277/
Use the FUSE register to get the list of active cores in the CPU
instead of using the CPU reset register, this is the recommended
method.
Also add code to mask the coremask with the default number of cores
for each processor series.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6275/
No change in logic, the changes are:
* cleanup some whitespace and comments
* remove confusing argument of SYS_CPU_COHERENT_BASE macro
* make the numerical labels in macros consistent
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6273/
Add MSI chip and MSIX chip definitions.
For MSI, we map the link interrupt to a MSI link IRQ which will
do a second level of dispatch based on the MSI status register.
The MSI chip definitions use the MSI enable register to enable
and disable the MSI irqs.
For MSI-X, we split the 32 available MSI-X vectors across the
four PCIe links (8 each). These PIC interrupts generate an IRQ
per link which uses a second level dispatch as well.
The MSI-X chip definition uses the standard functions to enable
and disable interrupts.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6270/
Boot log says:
pci 0000:00:0a.3: no compatible bridge window for [io 0x1000-0x103f]
pci 0000:00:0a.3: no compatible bridge window for [io 0x1100-0x110f]
The io resource starting point on Malta was modified by c5de50dada (MIPS:
Malta: Change start address to avoid conflicts.) to avoid conflicts with
ACPI and SMB devices. In fact, that was not needed (and now causing
southbridge ACPI missing) since 166c637075 (PCI: add pci_create_root_bus()
that accepts resource list) and 7c090e5bfa (mips/PCI: convert to
pci_scan_root_bus() for correct root bus resources) had already done the
correct fix.
This patch actually reverts the change made by c5de50dada. And with this
fix, log says:
pci 0000:00:0a.3: quirk: [io 0x1000-0x103f] claimed by PIIX4 ACPI
pci 0000:00:0a.3: quirk: [io 0x1100-0x110f] claimed by PIIX4 SMB
These things may not be used but as part of platform resources are better
off to be included.
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6037/
The platform data already available in tree for JZ4740 USB Device
Controller was previously used by an out-of-tree USB gadget driver
which was not relying on the musb driver and was written by Ingenic
and the Qi-Hardware community.
Update platform data for JZ4740 USB device controller to be used with
musb driver.
Signed-off-by: Apelete Seketeli <apelete@seketeli.net>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6265/
This patch cleans up the declaration of the resume function by replacing
void pointers with their correct types. The irrelevant & incorrect
comment preceeding the resume function is replaced by one documenting
its function.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6146/
