3 Commits

Author	SHA1	Message	Date
Lad Prabhakar	0b256c403d	dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock ... Add P0_DIV2 core clock required for CANFD module. CANFD core clock is sourced from P0_DIV2 referenced from HW manual Rev.0.50. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210719143811.2135-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2021-07-26 14:10:59 +02:00
Biju Das	c3e67ad6f5	dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions ... Update clock and reset definitions as per RZ/G2L_clock_list_r02_02.xlsx and RZ/G2L HW(Rev.0.50) manual. Update {GIC,IA55,SCIF} clock and reset entries in the CPG driver, and separate reset from module clocks in order to handle them efficiently. Update the SCIF0 clock and reset index in the SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-6-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20210626081344.5783-7-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20210626081344.5783-8-biju.das.jz@bp.renesas.com [geert: Squashed 3 commits] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2021-07-12 10:52:03 +02:00
Lad Prabhakar	4039213737	dt-bindings: clock: Add r9a07g044 CPG Clock Definitions ... Define RZ/G2L (R9A07G044) Clock Pulse Generator Core Clock and module clock outputs, as listed in Table 8.3 ("Clock List") of the RZ/G2L Hardware User's Manual (Rev.0.42, Feb.2021). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2021-06-10 15:23:37 +02:00