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mmc: sdhci-msm: Make tuning block table endian agnostic

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If we're tuning on a big-endian CPU we'll never determine we properly
tuned the device because we compare the data we received from the
controller with a table that assumes the CPU is little-endian.
Change the table to be an array of bytes instead of 32-bit words
so we can use memcmp() without needing to byte-swap every word
depending on the endianess of the CPU.

Cc: Asutosh Das <asutoshd@codeaurora.org>
Cc: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Reviewed-by: Georgi Djakov <gdjakov@mm-sol.com>
Fixes: 415b5a75da "mmc: sdhci-msm: Add platform_execute_tuning implementation"
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Stephen Boyd
2014-09-22 12:26:09 -07:00
committed by Ulf Hansson
parent d4d1144908
commit ffed1b94cb
1 changed files with 27 additions and 15 deletions
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42
drivers/mmc/host/sdhci-msm.c
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@@ -46,22 +46,34 @@
#define CMUX_SHIFT_PHASE_SHIFT 24 #define CMUX_SHIFT_PHASE_SHIFT 24
#define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT) #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
static const u32 tuning_block_64[] = { static const u8 tuning_block_64[] = {
0x00ff0fff, 0xccc3ccff, 0xffcc3cc3, 0xeffefffe, 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
0xddffdfff, 0xfbfffbff, 0xff7fffbf, 0xefbdf777, 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
0xf0fff0ff, 0x3cccfc0f, 0xcfcc33cc, 0xeeffefff, 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
0xfdfffdff, 0xffbfffdf, 0xfff7ffbb, 0xde7b7ff7 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
}; };
static const u32 tuning_block_128[] = { static const u8 tuning_block_128[] = {
0xff00ffff, 0x0000ffff, 0xccccffff, 0xcccc33cc, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
0xcc3333cc, 0xffffcccc, 0xffffeeff, 0xffeeeeff, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
0xffddffff, 0xddddffff, 0xbbffffff, 0xbbffffff, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
0xffffffbb, 0xffffff77, 0x77ff7777, 0xffeeddbb, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
0x00ffffff, 0x00ffffff, 0xccffff00, 0xcc33cccc, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
0x3333cccc, 0xffcccccc, 0xffeeffff, 0xeeeeffff, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
0xddffffff, 0xddffffff, 0xffffffdd, 0xffffffbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
0xffffbbbb, 0xffff77ff, 0xff7777ff, 0xeeddbb77 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
}; };
struct sdhci_msm_host { struct sdhci_msm_host {
@@ -358,7 +370,7 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
{ {
int tuning_seq_cnt = 3; int tuning_seq_cnt = 3;
u8 phase, *data_buf, tuned_phases[16], tuned_phase_cnt = 0; u8 phase, *data_buf, tuned_phases[16], tuned_phase_cnt = 0;
const u32 *tuning_block_pattern = tuning_block_64; const u8 *tuning_block_pattern = tuning_block_64;
int size = sizeof(tuning_block_64); /* Pattern size in bytes */ int size = sizeof(tuning_block_64); /* Pattern size in bytes */
int rc; int rc;
struct mmc_host *mmc = host->mmc; struct mmc_host *mmc = host->mmc;