forked from Minki/linux
kvm: mmu: don't set the present bit unconditionally
To support execute only mappings on behalf of L1 hypervisors, we need to teach set_spte() to honor all three of L1's XWR bits. As a start, add a new variable "shadow_present_mask" that will be set for non-EPT shadow paging and clear for EPT. Signed-off-by: Bandan Das <bsd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -1031,7 +1031,7 @@ void kvm_mmu_setup(struct kvm_vcpu *vcpu);
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void kvm_mmu_init_vm(struct kvm *kvm);
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void kvm_mmu_uninit_vm(struct kvm *kvm);
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void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
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u64 dirty_mask, u64 nx_mask, u64 x_mask);
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u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask);
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void kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
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void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
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@ -175,6 +175,7 @@ static u64 __read_mostly shadow_user_mask;
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static u64 __read_mostly shadow_accessed_mask;
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static u64 __read_mostly shadow_dirty_mask;
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static u64 __read_mostly shadow_mmio_mask;
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static u64 __read_mostly shadow_present_mask;
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static void mmu_spte_set(u64 *sptep, u64 spte);
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static void mmu_free_roots(struct kvm_vcpu *vcpu);
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@ -282,13 +283,14 @@ static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
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}
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void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
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u64 dirty_mask, u64 nx_mask, u64 x_mask)
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u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask)
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{
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shadow_user_mask = user_mask;
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shadow_accessed_mask = accessed_mask;
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shadow_dirty_mask = dirty_mask;
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shadow_nx_mask = nx_mask;
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shadow_x_mask = x_mask;
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shadow_present_mask = p_mask;
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}
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EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
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@ -2245,10 +2247,9 @@ static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
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{
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u64 spte;
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BUILD_BUG_ON(VMX_EPT_READABLE_MASK != PT_PRESENT_MASK ||
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VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
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BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
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spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
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spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK |
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shadow_user_mask | shadow_x_mask | shadow_accessed_mask;
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mmu_spte_set(sptep, spte);
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@ -2515,13 +2516,13 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
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gfn_t gfn, kvm_pfn_t pfn, bool speculative,
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bool can_unsync, bool host_writable)
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{
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u64 spte;
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u64 spte = 0;
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int ret = 0;
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if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
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return 0;
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spte = PT_PRESENT_MASK;
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spte |= shadow_present_mask;
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if (!speculative)
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spte |= shadow_accessed_mask;
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@ -6473,6 +6473,7 @@ static __init int hardware_setup(void)
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(enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
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(enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
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0ull, VMX_EPT_EXECUTABLE_MASK);
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0ull, VMX_EPT_EXECUTABLE_MASK, VMX_EPT_READABLE_MASK);
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ept_set_mmio_spte_mask();
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kvm_enable_tdp();
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} else
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@ -5878,8 +5878,8 @@ int kvm_arch_init(void *opaque)
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kvm_x86_ops = ops;
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kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
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PT_DIRTY_MASK, PT64_NX_MASK, 0);
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PT_DIRTY_MASK, PT64_NX_MASK, 0,
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PT_PRESENT_MASK);
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kvm_timer_init();
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perf_register_guest_info_callbacks(&kvm_guest_cbs);
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