octeontx2-af: NIX AQ instruction enqueue support
Add support for a RVU PF/VF to submit instructions to NIX AQ via mbox. Instructions can be to init/write/read RQ/SQ/CQ/RSS contexts. In case of read, context will be returned as part of response to the mbox msg received. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sunil Goutham
committed by
David S. Miller
David S. Miller
parent
709a4f0c25
commit
ffb0abd7e9
@@ -426,6 +426,424 @@ struct nix_aq_res_s {
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u64 reserved_64_127; /* W1 */
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};
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/* NIX Completion queue context structure */
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struct nix_cq_ctx_s {
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u64 base;
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#if defined(__BIG_ENDIAN_BITFIELD) /* W1 */
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u64 wrptr : 20;
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u64 avg_con : 9;
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u64 cint_idx : 7;
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u64 cq_err : 1;
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u64 qint_idx : 7;
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u64 rsvd_81_83 : 3;
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u64 bpid : 9;
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u64 rsvd_69_71 : 3;
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u64 bp_ena : 1;
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u64 rsvd_64_67 : 4;
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#else
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u64 rsvd_64_67 : 4;
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u64 bp_ena : 1;
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u64 rsvd_69_71 : 3;
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u64 bpid : 9;
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u64 rsvd_81_83 : 3;
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u64 qint_idx : 7;
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u64 cq_err : 1;
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u64 cint_idx : 7;
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u64 avg_con : 9;
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u64 wrptr : 20;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W2 */
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u64 update_time : 16;
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u64 avg_level : 8;
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u64 head : 20;
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u64 tail : 20;
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#else
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u64 tail : 20;
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u64 head : 20;
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u64 avg_level : 8;
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u64 update_time : 16;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W3 */
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u64 cq_err_int_ena : 8;
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u64 cq_err_int : 8;
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u64 qsize : 4;
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u64 rsvd_233_235 : 3;
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u64 caching : 1;
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u64 substream : 20;
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u64 rsvd_210_211 : 2;
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u64 ena : 1;
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u64 drop_ena : 1;
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u64 drop : 8;
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u64 dp : 8;
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#else
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u64 dp : 8;
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u64 drop : 8;
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u64 drop_ena : 1;
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u64 ena : 1;
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u64 rsvd_210_211 : 2;
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u64 substream : 20;
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u64 caching : 1;
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u64 rsvd_233_235 : 3;
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u64 qsize : 4;
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u64 cq_err_int : 8;
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u64 cq_err_int_ena : 8;
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#endif
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};
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/* NIX Receive queue context structure */
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struct nix_rq_ctx_s {
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#if defined(__BIG_ENDIAN_BITFIELD) /* W0 */
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u64 wqe_aura : 20;
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u64 substream : 20;
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u64 cq : 20;
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u64 ena_wqwd : 1;
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u64 ipsech_ena : 1;
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u64 sso_ena : 1;
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u64 ena : 1;
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#else
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u64 ena : 1;
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u64 sso_ena : 1;
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u64 ipsech_ena : 1;
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u64 ena_wqwd : 1;
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u64 cq : 20;
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u64 substream : 20;
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u64 wqe_aura : 20;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W1 */
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u64 rsvd_127_122 : 6;
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u64 lpb_drop_ena : 1;
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u64 spb_drop_ena : 1;
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u64 xqe_drop_ena : 1;
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u64 wqe_caching : 1;
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u64 pb_caching : 2;
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u64 sso_tt : 2;
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u64 sso_grp : 10;
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u64 lpb_aura : 20;
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u64 spb_aura : 20;
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#else
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u64 spb_aura : 20;
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u64 lpb_aura : 20;
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u64 sso_grp : 10;
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u64 sso_tt : 2;
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u64 pb_caching : 2;
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u64 wqe_caching : 1;
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u64 xqe_drop_ena : 1;
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u64 spb_drop_ena : 1;
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u64 lpb_drop_ena : 1;
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u64 rsvd_127_122 : 6;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W2 */
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u64 xqe_hdr_split : 1;
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u64 xqe_imm_copy : 1;
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u64 rsvd_189_184 : 6;
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u64 xqe_imm_size : 6;
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u64 later_skip : 6;
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u64 rsvd_171 : 1;
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u64 first_skip : 7;
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u64 lpb_sizem1 : 12;
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u64 spb_ena : 1;
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u64 rsvd_150_148 : 3;
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u64 wqe_skip : 2;
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u64 spb_sizem1 : 6;
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u64 rsvd_139_128 : 12;
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#else
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u64 rsvd_139_128 : 12;
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u64 spb_sizem1 : 6;
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u64 wqe_skip : 2;
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u64 rsvd_150_148 : 3;
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u64 spb_ena : 1;
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u64 lpb_sizem1 : 12;
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u64 first_skip : 7;
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u64 rsvd_171 : 1;
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u64 later_skip : 6;
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u64 xqe_imm_size : 6;
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u64 rsvd_189_184 : 6;
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u64 xqe_imm_copy : 1;
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u64 xqe_hdr_split : 1;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W3 */
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u64 spb_pool_pass : 8;
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u64 spb_pool_drop : 8;
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u64 spb_aura_pass : 8;
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u64 spb_aura_drop : 8;
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u64 wqe_pool_pass : 8;
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u64 wqe_pool_drop : 8;
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u64 xqe_pass : 8;
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u64 xqe_drop : 8;
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#else
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u64 xqe_drop : 8;
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u64 xqe_pass : 8;
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u64 wqe_pool_drop : 8;
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u64 wqe_pool_pass : 8;
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u64 spb_aura_drop : 8;
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u64 spb_aura_pass : 8;
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u64 spb_pool_drop : 8;
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u64 spb_pool_pass : 8;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W4 */
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u64 rsvd_319_315 : 5;
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u64 qint_idx : 7;
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u64 rq_int_ena : 8;
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u64 rq_int : 8;
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u64 rsvd_291_288 : 4;
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u64 lpb_pool_pass : 8;
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u64 lpb_pool_drop : 8;
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u64 lpb_aura_pass : 8;
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u64 lpb_aura_drop : 8;
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#else
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u64 lpb_aura_drop : 8;
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u64 lpb_aura_pass : 8;
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u64 lpb_pool_drop : 8;
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u64 lpb_pool_pass : 8;
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u64 rsvd_291_288 : 4;
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u64 rq_int : 8;
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u64 rq_int_ena : 8;
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u64 qint_idx : 7;
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u64 rsvd_319_315 : 5;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W5 */
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u64 rsvd_383_366 : 18;
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u64 flow_tagw : 6;
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u64 bad_utag : 8;
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u64 good_utag : 8;
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u64 ltag : 24;
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#else
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u64 ltag : 24;
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u64 good_utag : 8;
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u64 bad_utag : 8;
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u64 flow_tagw : 6;
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u64 rsvd_383_366 : 18;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W6 */
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u64 rsvd_447_432 : 16;
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u64 octs : 48;
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#else
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u64 octs : 48;
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u64 rsvd_447_432 : 16;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W7 */
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u64 rsvd_511_496 : 16;
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u64 pkts : 48;
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#else
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u64 pkts : 48;
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u64 rsvd_511_496 : 16;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W8 */
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u64 rsvd_575_560 : 16;
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u64 drop_octs : 48;
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#else
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u64 drop_octs : 48;
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u64 rsvd_575_560 : 16;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W9 */
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u64 rsvd_639_624 : 16;
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u64 drop_pkts : 48;
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#else
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u64 drop_pkts : 48;
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u64 rsvd_639_624 : 16;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W10 */
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u64 rsvd_703_688 : 16;
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u64 re_pkts : 48;
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#else
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u64 re_pkts : 48;
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u64 rsvd_703_688 : 16;
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#endif
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u64 rsvd_767_704; /* W11 */
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u64 rsvd_831_768; /* W12 */
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u64 rsvd_895_832; /* W13 */
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u64 rsvd_959_896; /* W14 */
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u64 rsvd_1023_960; /* W15 */
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};
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/* NIX sqe sizes */
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enum nix_maxsqesz {
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NIX_MAXSQESZ_W16 = 0x0,
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NIX_MAXSQESZ_W8 = 0x1,
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};
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/* NIX SQB caching type */
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enum nix_stype {
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NIX_STYPE_STF = 0x0,
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NIX_STYPE_STT = 0x1,
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NIX_STYPE_STP = 0x2,
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};
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/* NIX Send queue context structure */
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struct nix_sq_ctx_s {
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#if defined(__BIG_ENDIAN_BITFIELD) /* W0 */
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u64 sqe_way_mask : 16;
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u64 cq : 20;
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u64 sdp_mcast : 1;
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u64 substream : 20;
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u64 qint_idx : 6;
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u64 ena : 1;
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#else
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u64 ena : 1;
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u64 qint_idx : 6;
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u64 substream : 20;
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u64 sdp_mcast : 1;
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u64 cq : 20;
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u64 sqe_way_mask : 16;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W1 */
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u64 sqb_count : 16;
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u64 default_chan : 12;
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u64 smq_rr_quantum : 24;
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u64 sso_ena : 1;
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u64 xoff : 1;
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u64 cq_ena : 1;
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u64 smq : 9;
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#else
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u64 smq : 9;
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u64 cq_ena : 1;
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u64 xoff : 1;
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u64 sso_ena : 1;
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u64 smq_rr_quantum : 24;
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u64 default_chan : 12;
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u64 sqb_count : 16;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W2 */
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u64 rsvd_191 : 1;
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u64 sqe_stype : 2;
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u64 sq_int_ena : 8;
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u64 sq_int : 8;
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u64 sqb_aura : 20;
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u64 smq_rr_count : 25;
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#else
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u64 smq_rr_count : 25;
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u64 sqb_aura : 20;
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u64 sq_int : 8;
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u64 sq_int_ena : 8;
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u64 sqe_stype : 2;
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u64 rsvd_191 : 1;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W3 */
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u64 rsvd_255_253 : 3;
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u64 smq_next_sq_vld : 1;
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u64 smq_pend : 1;
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u64 smenq_next_sqb_vld : 1;
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u64 head_offset : 6;
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u64 smenq_offset : 6;
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u64 tail_offset : 6;
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u64 smq_lso_segnum : 8;
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u64 smq_next_sq : 20;
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u64 mnq_dis : 1;
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u64 lmt_dis : 1;
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u64 cq_limit : 8;
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u64 max_sqe_size : 2;
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#else
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u64 max_sqe_size : 2;
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u64 cq_limit : 8;
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u64 lmt_dis : 1;
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u64 mnq_dis : 1;
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u64 smq_next_sq : 20;
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u64 smq_lso_segnum : 8;
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u64 tail_offset : 6;
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u64 smenq_offset : 6;
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u64 head_offset : 6;
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u64 smenq_next_sqb_vld : 1;
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u64 smq_pend : 1;
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u64 smq_next_sq_vld : 1;
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u64 rsvd_255_253 : 3;
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#endif
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u64 next_sqb : 64;/* W4 */
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u64 tail_sqb : 64;/* W5 */
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u64 smenq_sqb : 64;/* W6 */
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u64 smenq_next_sqb : 64;/* W7 */
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u64 head_sqb : 64;/* W8 */
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#if defined(__BIG_ENDIAN_BITFIELD) /* W9 */
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u64 rsvd_639_630 : 10;
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u64 vfi_lso_vld : 1;
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u64 vfi_lso_vlan1_ins_ena : 1;
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u64 vfi_lso_vlan0_ins_ena : 1;
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u64 vfi_lso_mps : 14;
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u64 vfi_lso_sb : 8;
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u64 vfi_lso_sizem1 : 3;
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u64 vfi_lso_total : 18;
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u64 rsvd_583_576 : 8;
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#else
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u64 rsvd_583_576 : 8;
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u64 vfi_lso_total : 18;
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u64 vfi_lso_sizem1 : 3;
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u64 vfi_lso_sb : 8;
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u64 vfi_lso_mps : 14;
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u64 vfi_lso_vlan0_ins_ena : 1;
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u64 vfi_lso_vlan1_ins_ena : 1;
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u64 vfi_lso_vld : 1;
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u64 rsvd_639_630 : 10;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W10 */
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u64 rsvd_703_658 : 46;
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u64 scm_lso_rem : 18;
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#else
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u64 scm_lso_rem : 18;
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u64 rsvd_703_658 : 46;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W11 */
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u64 rsvd_767_752 : 16;
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u64 octs : 48;
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#else
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u64 octs : 48;
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u64 rsvd_767_752 : 16;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W12 */
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u64 rsvd_831_816 : 16;
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u64 pkts : 48;
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#else
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u64 pkts : 48;
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u64 rsvd_831_816 : 16;
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#endif
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u64 rsvd_895_832 : 64;/* W13 */
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#if defined(__BIG_ENDIAN_BITFIELD) /* W14 */
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u64 rsvd_959_944 : 16;
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u64 dropped_octs : 48;
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#else
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u64 dropped_octs : 48;
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u64 rsvd_959_944 : 16;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W15 */
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u64 rsvd_1023_1008 : 16;
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u64 dropped_pkts : 48;
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#else
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u64 dropped_pkts : 48;
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u64 rsvd_1023_1008 : 16;
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#endif
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};
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/* NIX Receive side scaling entry structure*/
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struct nix_rsse_s {
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#if defined(__BIG_ENDIAN_BITFIELD)
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uint32_t reserved_20_31 : 12;
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uint32_t rq : 20;
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#else
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uint32_t rq : 20;
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uint32_t reserved_20_31 : 12;
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#endif
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};
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/* NIX receive multicast/mirror entry structure */
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struct nix_rx_mce_s {
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#if defined(__BIG_ENDIAN_BITFIELD) /* W0 */
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uint64_t next : 16;
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uint64_t pf_func : 16;
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uint64_t rsvd_31_24 : 8;
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uint64_t index : 20;
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uint64_t eol : 1;
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uint64_t rsvd_2 : 1;
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uint64_t op : 2;
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#else
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uint64_t op : 2;
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uint64_t rsvd_2 : 1;
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uint64_t eol : 1;
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uint64_t index : 20;
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uint64_t rsvd_31_24 : 8;
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uint64_t pf_func : 16;
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uint64_t next : 16;
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#endif
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};
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enum nix_lsoalg {
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NIX_LSOALG_NOP,
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NIX_LSOALG_ADD_SEGNUM,
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