[IrDA] stir4200: removing undocumented bits handling

FIFOCTL_RXERR and FIFOCTL_TXERR are undocumented bits, according to the
Sigmatel datasheet. We should thus not take any assumption on their values
and semantics.

Problem spotted by andrzej zaborowski <balrogg@gmail.com>
Signed-off-by: Samuel Ortiz <samuel@sortiz.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Samuel Ortiz 2006-09-27 22:50:06 -07:00 committed by David S. Miller
parent 895de090d4
commit febac9b937

View File

@ -149,8 +149,6 @@ enum StirFifoCtlMask {
FIFOCTL_DIR = 0x10,
FIFOCTL_CLR = 0x08,
FIFOCTL_EMPTY = 0x04,
FIFOCTL_RXERR = 0x02,
FIFOCTL_TXERR = 0x01,
};
enum StirDiagMask {
@ -615,19 +613,6 @@ static int fifo_txwait(struct stir_cb *stir, int space)
pr_debug("fifo status 0x%lx count %lu\n", status, count);
/* error when receive/transmit fifo gets confused */
if (status & FIFOCTL_RXERR) {
stir->stats.rx_fifo_errors++;
stir->stats.rx_errors++;
break;
}
if (status & FIFOCTL_TXERR) {
stir->stats.tx_fifo_errors++;
stir->stats.tx_errors++;
break;
}
/* is fifo receiving already, or empty */
if (!(status & FIFOCTL_DIR)
|| (status & FIFOCTL_EMPTY))