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drm/i915: Handle all MCR ranges

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The bspec documents multiple MCR ranges; make sure they're all captured
by the driver.

Bspec: 13991, 52079
Fixes: 592a7c5e08 ("drm/i915: Extend non readable mcr range")
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200311162300.1838847-2-matthew.d.roper@intel.com
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
(cherry picked from commit 415d126997)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Matt Roper 2020-03-11 09:22:55 -07:00 committed by Jani Nikula
parent c09f6b4d08
commit fe8b7085ca
1 changed files with 22 additions and 3 deletions
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25
drivers/gpu/drm/i915/gt/intel_workarounds.c
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@ -1529,15 +1529,34 @@ err_obj:
return ERR_PTR(err);
}
static const struct {
u32 start;
u32 end;
} mcr_ranges_gen8[] = {
{ .start = 0x5500, .end = 0x55ff },
{ .start = 0x7000, .end = 0x7fff },
{ .start = 0x9400, .end = 0x97ff },
{ .start = 0xb000, .end = 0xb3ff },
{ .start = 0xe000, .end = 0xe7ff },
{},
};
static bool mcr_range(struct drm_i915_private *i915, u32 offset)
{
int i;
if (INTEL_GEN(i915) < 8)
return false;
/*
* Registers in this range are affected by the MCR selector
* Registers in these ranges are affected by the MCR selector
* which only controls CPU initiated MMIO. Routing does not
* work for CS access so we cannot verify them on this path.
*/
if (INTEL_GEN(i915) >= 8 && (offset >= 0xb000 && offset <= 0xb4ff))
return true;
for (i = 0; mcr_ranges_gen8[i].start; i++)
if (offset >= mcr_ranges_gen8[i].start &&
offset <= mcr_ranges_gen8[i].end)
return true;
return false;
}