drm/amd/display: Modify plane removal sequence to avoid hangs.

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dillon Varone
2022-02-10 18:17:39 -05:00
committed by Alex Deucher
parent 7952fa0d3e
commit fe5e8f07fc
2 changed files with 6 additions and 6 deletions

View File

@@ -107,7 +107,7 @@ void dcn10_lock_all_pipes(struct dc *dc,
* (un)locking. Also skip if pipe is disabled. * (un)locking. Also skip if pipe is disabled.
*/ */
if (pipe_ctx->top_pipe || if (pipe_ctx->top_pipe ||
!pipe_ctx->stream || !pipe_ctx->plane_state || !pipe_ctx->stream ||
!tg->funcs->is_tg_enabled(tg)) !tg->funcs->is_tg_enabled(tg))
continue; continue;

View File

@@ -931,10 +931,6 @@ void hubp2_set_blank_regs(struct hubp *hubp, bool blank)
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
uint32_t blank_en = blank ? 1 : 0; uint32_t blank_en = blank ? 1 : 0;
REG_UPDATE_2(DCHUBP_CNTL,
HUBP_BLANK_EN, blank_en,
HUBP_TTU_DISABLE, blank_en);
if (blank) { if (blank) {
uint32_t reg_val = REG_READ(DCHUBP_CNTL); uint32_t reg_val = REG_READ(DCHUBP_CNTL);
@@ -947,9 +943,13 @@ void hubp2_set_blank_regs(struct hubp *hubp, bool blank)
*/ */
REG_WAIT(DCHUBP_CNTL, REG_WAIT(DCHUBP_CNTL,
HUBP_NO_OUTSTANDING_REQ, 1, HUBP_NO_OUTSTANDING_REQ, 1,
1, 200); 1, 100000);
} }
} }
REG_UPDATE_2(DCHUBP_CNTL,
HUBP_BLANK_EN, blank_en,
HUBP_TTU_DISABLE, 0);
} }
void hubp2_cursor_set_position( void hubp2_cursor_set_position(