forked from Minki/linux
pinctrl: sh-pfc: Updates for v4.13
- Add PWM, AVB MDIO/MII, and sound pin groups on R-Car M3-W, - Add support for RZ/G1M and RZ/G1E, - Small fixes and cleanups. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZLAvNAAoJEEgEtLw/Ve77NxAQAIH8Gxvb+UHWAvMWlJFZfVu8 HCjGAJcx+pyUh2SWBhE5Xd10ovpN0tI/AP32Ry1rBajiTrhh1oGUBssPc6BIYD8H ZEfMZLEU0hevnxAl2wVoXbuAzr4Ur/CZ5wBah+8P9LpdXYZLRDG6UKrNH/BKoHYY RjmKndQObBIw30wRFQl6HHvPA5G9uf+LguTU+mmJRPMaPWPgvDVPqyJ/jeVzo5If 6459xU84fPX3XDEDhIoQ6K7FmBsVMpDh5ohWguKaIWirWFr1myyunFbycH0T70l4 kYgRDuiz0YN5S3Jbl9TQkzcI51i73qkSTvOqVDy3BpvuEP6IKcwOgOqf1iXfUxhx olluP0Z6wBNSi3Ck0s1yWNWK1JOsb9OFqf/tmS3XlOl4t970bDa4uvXrjz6Z8kzN AFDpTc6SgwRreNq2nklp73UkxCovhPrXq/buKnTs/jXJjWgkMPGfvByhn60ngUzm ivsd/MjsTJ0ZmZgbY2cCChznY7xTkpQGB+WuR6UXIrVqeBbR8HkbZqAdFsM6oCwE r0i2Gnzq0hifv5XIG6p2m8pfLiiSum88mPupLGK1zPfVosEYQbCW2K9EGXtLt87u RIs4N2tC3pgiyUnMm19u8vylo6D+jWOj9QjTvXchNyoL67iJEcv8dZ5BcS13OSiR QKNk4G2FywO9pklsELFy =JT2m -----END PGP SIGNATURE----- Merge tag 'sh-pfc-for-v4.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.13 - Add PWM, AVB MDIO/MII, and sound pin groups on R-Car M3-W, - Add support for RZ/G1M and RZ/G1E, - Small fixes and cleanups.
This commit is contained in:
Linus Walleij
commit
fe5984112e
@ -13,6 +13,8 @@ Required Properties:
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- "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
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- "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
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- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
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- "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
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- "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
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- "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
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- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
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- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
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@ -34,6 +34,16 @@ config PINCTRL_PFC_R8A7740
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depends on ARCH_R8A7740
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select PINCTRL_SH_PFC_GPIO
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config PINCTRL_PFC_R8A7743
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def_bool y
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depends on ARCH_R8A7743
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_R8A7745
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def_bool y
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depends on ARCH_R8A7745
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_R8A7778
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def_bool y
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depends on ARCH_R8A7778
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@ -3,6 +3,8 @@ obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o
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obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o
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obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7743) += pfc-r8a7791.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7745) += pfc-r8a7794.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
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@ -485,6 +485,18 @@ static const struct of_device_id sh_pfc_of_table[] = {
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.data = &r8a7740_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A7743
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{
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.compatible = "renesas,pfc-r8a7743",
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.data = &r8a7743_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A7745
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{
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.compatible = "renesas,pfc-r8a7745",
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.data = &r8a7745_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A7778
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{
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.compatible = "renesas,pfc-r8a7778",
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -192,8 +192,8 @@
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#define GPSR6_9 F_(SSI_WS4, IP14_27_24)
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#define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
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#define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
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#define GPSR6_6 F_(SSI_WS34, IP14_15_12)
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#define GPSR6_5 F_(SSI_SCK34, IP14_11_8)
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#define GPSR6_6 F_(SSI_WS349, IP14_15_12)
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#define GPSR6_5 F_(SSI_SCK349, IP14_11_8)
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#define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
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#define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
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#define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
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@ -328,8 +328,8 @@
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#define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP14_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP14_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP14_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP14_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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@ -1256,11 +1256,11 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
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PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
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PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK34),
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PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK349),
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PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
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PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
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PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS34),
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PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS349),
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PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
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PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
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PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
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@ -3650,12 +3650,12 @@ static const unsigned int ssi3_data_pins[] = {
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static const unsigned int ssi3_data_mux[] = {
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SSI_SDATA3_MARK,
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};
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static const unsigned int ssi34_ctrl_pins[] = {
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static const unsigned int ssi349_ctrl_pins[] = {
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/* SCK, WS */
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RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
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};
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static const unsigned int ssi34_ctrl_mux[] = {
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SSI_SCK34_MARK, SSI_WS34_MARK,
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static const unsigned int ssi349_ctrl_mux[] = {
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SSI_SCK349_MARK, SSI_WS349_MARK,
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};
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static const unsigned int ssi4_data_pins[] = {
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/* SDATA */
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@ -4063,7 +4063,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(ssi2_ctrl_a),
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SH_PFC_PIN_GROUP(ssi2_ctrl_b),
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SH_PFC_PIN_GROUP(ssi3_data),
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SH_PFC_PIN_GROUP(ssi34_ctrl),
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SH_PFC_PIN_GROUP(ssi349_ctrl),
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SH_PFC_PIN_GROUP(ssi4_data),
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SH_PFC_PIN_GROUP(ssi4_ctrl),
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SH_PFC_PIN_GROUP(ssi5_data),
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@ -4509,7 +4509,7 @@ static const char * const ssi_groups[] = {
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"ssi2_ctrl_a",
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"ssi2_ctrl_b",
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"ssi3_data",
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"ssi34_ctrl",
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"ssi349_ctrl",
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"ssi4_data",
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"ssi4_ctrl",
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"ssi5_data",
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@ -5356,8 +5356,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
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{ RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
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{ RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
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{ RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
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{ RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */
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{ RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */
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{ RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
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{ RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
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{ RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
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{ RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
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} },
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@ -5604,8 +5604,8 @@ static const struct sh_pfc_bias_info bias_info[] = {
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{ RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
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{ RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
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{ RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
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{ RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
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{ RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
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{ RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */
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{ RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */
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{ RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
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{ RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
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{ RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
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@ -193,8 +193,8 @@
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#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
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#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
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#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
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#define GPSR6_6 F_(SSI_WS34, IP15_15_12)
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#define GPSR6_5 F_(SSI_SCK34, IP15_11_8)
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#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
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#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
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#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
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#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
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#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
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@ -339,8 +339,8 @@
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#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP15_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP15_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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@ -1315,11 +1315,11 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
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PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
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PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK34),
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PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
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PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
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PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
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PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS34),
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PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
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PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
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PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
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PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
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@ -2653,8 +2653,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
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{ RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
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{ RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
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{ RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
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{ RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */
|
||||
{ RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */
|
||||
{ RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
|
||||
{ RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
|
||||
{ RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
|
||||
{ RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
|
||||
} },
|
||||
@ -2900,8 +2900,8 @@ static const struct sh_pfc_bias_info bias_info[] = {
|
||||
{ RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
|
||||
{ RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
|
||||
{ RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
|
||||
{ RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
|
||||
{ RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
|
||||
{ RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */
|
||||
{ RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */
|
||||
{ RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
|
||||
{ RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
|
||||
{ RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
|
||||
|
||||
@ -199,13 +199,13 @@
|
||||
#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
|
||||
#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
|
||||
#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
|
||||
#define GPSR6_6 F_(SSI_WS34, IP15_15_12)
|
||||
#define GPSR6_5 F_(SSI_SCK34, IP15_11_8)
|
||||
#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
|
||||
#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
|
||||
#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
|
||||
#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
|
||||
#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
|
||||
#define GPSR6_1 F_(SSI_WS0129, IP14_27_24)
|
||||
#define GPSR6_0 F_(SSI_SCK0129, IP14_23_20)
|
||||
#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
|
||||
#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
|
||||
|
||||
/* GPSR7 */
|
||||
#define GPSR7_3 FM(GP7_03)
|
||||
@ -338,15 +338,15 @@
|
||||
#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP14_23_20 FM(SSI_SCK0129) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP14_27_24 FM(SSI_WS0129) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
||||
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
|
||||
#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP15_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP15_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
@ -1304,10 +1304,10 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK0129),
|
||||
PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
|
||||
PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS0129),
|
||||
PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
|
||||
PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
|
||||
@ -1319,11 +1319,11 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
|
||||
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK34),
|
||||
PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
|
||||
PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
|
||||
PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS34),
|
||||
PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
|
||||
PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
|
||||
PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
|
||||
PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
|
||||
@ -1582,6 +1582,128 @@ static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
|
||||
};
|
||||
|
||||
/* - AUDIO CLOCK ------------------------------------------------------------ */
|
||||
static const unsigned int audio_clk_a_a_pins[] = {
|
||||
/* CLK A */
|
||||
RCAR_GP_PIN(6, 22),
|
||||
};
|
||||
static const unsigned int audio_clk_a_a_mux[] = {
|
||||
AUDIO_CLKA_A_MARK,
|
||||
};
|
||||
static const unsigned int audio_clk_a_b_pins[] = {
|
||||
/* CLK A */
|
||||
RCAR_GP_PIN(5, 4),
|
||||
};
|
||||
static const unsigned int audio_clk_a_b_mux[] = {
|
||||
AUDIO_CLKA_B_MARK,
|
||||
};
|
||||
static const unsigned int audio_clk_a_c_pins[] = {
|
||||
/* CLK A */
|
||||
RCAR_GP_PIN(5, 19),
|
||||
};
|
||||
static const unsigned int audio_clk_a_c_mux[] = {
|
||||
AUDIO_CLKA_C_MARK,
|
||||
};
|
||||
static const unsigned int audio_clk_b_a_pins[] = {
|
||||
/* CLK B */
|
||||
RCAR_GP_PIN(5, 12),
|
||||
};
|
||||
static const unsigned int audio_clk_b_a_mux[] = {
|
||||
AUDIO_CLKB_A_MARK,
|
||||
};
|
||||
static const unsigned int audio_clk_b_b_pins[] = {
|
||||
/* CLK B */
|
||||
RCAR_GP_PIN(6, 23),
|
||||
};
|
||||
static const unsigned int audio_clk_b_b_mux[] = {
|
||||
AUDIO_CLKB_B_MARK,
|
||||
};
|
||||
static const unsigned int audio_clk_c_a_pins[] = {
|
||||
/* CLK C */
|
||||
RCAR_GP_PIN(5, 21),
|
||||
};
|
||||
static const unsigned int audio_clk_c_a_mux[] = {
|
||||
AUDIO_CLKC_A_MARK,
|
||||
};
|
||||
static const unsigned int audio_clk_c_b_pins[] = {
|
||||
/* CLK C */
|
||||
RCAR_GP_PIN(5, 0),
|
||||
};
|
||||
static const unsigned int audio_clk_c_b_mux[] = {
|
||||
AUDIO_CLKC_B_MARK,
|
||||
};
|
||||
static const unsigned int audio_clkout_a_pins[] = {
|
||||
/* CLKOUT */
|
||||
RCAR_GP_PIN(5, 18),
|
||||
};
|
||||
static const unsigned int audio_clkout_a_mux[] = {
|
||||
AUDIO_CLKOUT_A_MARK,
|
||||
};
|
||||
static const unsigned int audio_clkout_b_pins[] = {
|
||||
/* CLKOUT */
|
||||
RCAR_GP_PIN(6, 28),
|
||||
};
|
||||
static const unsigned int audio_clkout_b_mux[] = {
|
||||
AUDIO_CLKOUT_B_MARK,
|
||||
};
|
||||
static const unsigned int audio_clkout_c_pins[] = {
|
||||
/* CLKOUT */
|
||||
RCAR_GP_PIN(5, 3),
|
||||
};
|
||||
static const unsigned int audio_clkout_c_mux[] = {
|
||||
AUDIO_CLKOUT_C_MARK,
|
||||
};
|
||||
static const unsigned int audio_clkout_d_pins[] = {
|
||||
/* CLKOUT */
|
||||
RCAR_GP_PIN(5, 21),
|
||||
};
|
||||
static const unsigned int audio_clkout_d_mux[] = {
|
||||
AUDIO_CLKOUT_D_MARK,
|
||||
};
|
||||
static const unsigned int audio_clkout1_a_pins[] = {
|
||||
/* CLKOUT1 */
|
||||
RCAR_GP_PIN(5, 15),
|
||||
};
|
||||
static const unsigned int audio_clkout1_a_mux[] = {
|
||||
AUDIO_CLKOUT1_A_MARK,
|
||||
};
|
||||
static const unsigned int audio_clkout1_b_pins[] = {
|
||||
/* CLKOUT1 */
|
||||
RCAR_GP_PIN(6, 29),
|
||||
};
|
||||
static const unsigned int audio_clkout1_b_mux[] = {
|
||||
AUDIO_CLKOUT1_B_MARK,
|
||||
};
|
||||
static const unsigned int audio_clkout2_a_pins[] = {
|
||||
/* CLKOUT2 */
|
||||
RCAR_GP_PIN(5, 16),
|
||||
};
|
||||
static const unsigned int audio_clkout2_a_mux[] = {
|
||||
AUDIO_CLKOUT2_A_MARK,
|
||||
};
|
||||
static const unsigned int audio_clkout2_b_pins[] = {
|
||||
/* CLKOUT2 */
|
||||
RCAR_GP_PIN(6, 30),
|
||||
};
|
||||
static const unsigned int audio_clkout2_b_mux[] = {
|
||||
AUDIO_CLKOUT2_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int audio_clkout3_a_pins[] = {
|
||||
/* CLKOUT3 */
|
||||
RCAR_GP_PIN(5, 19),
|
||||
};
|
||||
static const unsigned int audio_clkout3_a_mux[] = {
|
||||
AUDIO_CLKOUT3_A_MARK,
|
||||
};
|
||||
static const unsigned int audio_clkout3_b_pins[] = {
|
||||
/* CLKOUT3 */
|
||||
RCAR_GP_PIN(6, 31),
|
||||
};
|
||||
static const unsigned int audio_clkout3_b_mux[] = {
|
||||
AUDIO_CLKOUT3_B_MARK,
|
||||
};
|
||||
|
||||
/* - EtherAVB --------------------------------------------------------------- */
|
||||
static const unsigned int avb_link_pins[] = {
|
||||
/* AVB_LINK */
|
||||
@ -1605,11 +1727,33 @@ static const unsigned int avb_phy_int_mux[] = {
|
||||
AVB_PHY_INT_MARK,
|
||||
};
|
||||
static const unsigned int avb_mdc_pins[] = {
|
||||
/* AVB_MDC */
|
||||
RCAR_GP_PIN(2, 9),
|
||||
/* AVB_MDC, AVB_MDIO */
|
||||
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
|
||||
};
|
||||
static const unsigned int avb_mdc_mux[] = {
|
||||
AVB_MDC_MARK,
|
||||
AVB_MDC_MARK, AVB_MDIO_MARK,
|
||||
};
|
||||
static const unsigned int avb_mii_pins[] = {
|
||||
/*
|
||||
* AVB_TX_CTL, AVB_TXC, AVB_TD0,
|
||||
* AVB_TD1, AVB_TD2, AVB_TD3,
|
||||
* AVB_RX_CTL, AVB_RXC, AVB_RD0,
|
||||
* AVB_RD1, AVB_RD2, AVB_RD3,
|
||||
* AVB_TXCREFCLK
|
||||
*/
|
||||
PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
|
||||
PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
|
||||
PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
|
||||
PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
|
||||
PIN_NUMBER('A', 12),
|
||||
|
||||
};
|
||||
static const unsigned int avb_mii_mux[] = {
|
||||
AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
|
||||
AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
|
||||
AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
|
||||
AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
|
||||
AVB_TXCREFCLK_MARK,
|
||||
};
|
||||
static const unsigned int avb_avtp_pps_pins[] = {
|
||||
/* AVB_AVTP_PPS */
|
||||
@ -2955,6 +3099,105 @@ static const unsigned int msiof3_rxd_e_mux[] = {
|
||||
MSIOF3_RXD_E_MARK,
|
||||
};
|
||||
|
||||
/* - PWM0 --------------------------------------------------------------------*/
|
||||
static const unsigned int pwm0_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 6),
|
||||
};
|
||||
static const unsigned int pwm0_mux[] = {
|
||||
PWM0_MARK,
|
||||
};
|
||||
/* - PWM1 --------------------------------------------------------------------*/
|
||||
static const unsigned int pwm1_a_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 7),
|
||||
};
|
||||
static const unsigned int pwm1_a_mux[] = {
|
||||
PWM1_A_MARK,
|
||||
};
|
||||
static const unsigned int pwm1_b_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(1, 8),
|
||||
};
|
||||
static const unsigned int pwm1_b_mux[] = {
|
||||
PWM1_B_MARK,
|
||||
};
|
||||
/* - PWM2 --------------------------------------------------------------------*/
|
||||
static const unsigned int pwm2_a_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 8),
|
||||
};
|
||||
static const unsigned int pwm2_a_mux[] = {
|
||||
PWM2_A_MARK,
|
||||
};
|
||||
static const unsigned int pwm2_b_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(1, 11),
|
||||
};
|
||||
static const unsigned int pwm2_b_mux[] = {
|
||||
PWM2_B_MARK,
|
||||
};
|
||||
/* - PWM3 --------------------------------------------------------------------*/
|
||||
static const unsigned int pwm3_a_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(1, 0),
|
||||
};
|
||||
static const unsigned int pwm3_a_mux[] = {
|
||||
PWM3_A_MARK,
|
||||
};
|
||||
static const unsigned int pwm3_b_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 2),
|
||||
};
|
||||
static const unsigned int pwm3_b_mux[] = {
|
||||
PWM3_B_MARK,
|
||||
};
|
||||
/* - PWM4 --------------------------------------------------------------------*/
|
||||
static const unsigned int pwm4_a_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(1, 1),
|
||||
};
|
||||
static const unsigned int pwm4_a_mux[] = {
|
||||
PWM4_A_MARK,
|
||||
};
|
||||
static const unsigned int pwm4_b_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 3),
|
||||
};
|
||||
static const unsigned int pwm4_b_mux[] = {
|
||||
PWM4_B_MARK,
|
||||
};
|
||||
/* - PWM5 --------------------------------------------------------------------*/
|
||||
static const unsigned int pwm5_a_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(1, 2),
|
||||
};
|
||||
static const unsigned int pwm5_a_mux[] = {
|
||||
PWM5_A_MARK,
|
||||
};
|
||||
static const unsigned int pwm5_b_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 4),
|
||||
};
|
||||
static const unsigned int pwm5_b_mux[] = {
|
||||
PWM5_B_MARK,
|
||||
};
|
||||
/* - PWM6 --------------------------------------------------------------------*/
|
||||
static const unsigned int pwm6_a_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(1, 3),
|
||||
};
|
||||
static const unsigned int pwm6_a_mux[] = {
|
||||
PWM6_A_MARK,
|
||||
};
|
||||
static const unsigned int pwm6_b_pins[] = {
|
||||
/* PWM */
|
||||
RCAR_GP_PIN(2, 5),
|
||||
};
|
||||
static const unsigned int pwm6_b_mux[] = {
|
||||
PWM6_B_MARK,
|
||||
};
|
||||
|
||||
/* - SCIF0 ------------------------------------------------------------------ */
|
||||
static const unsigned int scif0_data_pins[] = {
|
||||
/* RX, TX */
|
||||
@ -3376,11 +3619,206 @@ static const unsigned int sdhi3_ds_mux[] = {
|
||||
SD3_DS_MARK,
|
||||
};
|
||||
|
||||
/* - SSI -------------------------------------------------------------------- */
|
||||
static const unsigned int ssi0_data_pins[] = {
|
||||
/* SDATA */
|
||||
RCAR_GP_PIN(6, 2),
|
||||
};
|
||||
static const unsigned int ssi0_data_mux[] = {
|
||||
SSI_SDATA0_MARK,
|
||||
};
|
||||
static const unsigned int ssi01239_ctrl_pins[] = {
|
||||
/* SCK, WS */
|
||||
RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
|
||||
};
|
||||
static const unsigned int ssi01239_ctrl_mux[] = {
|
||||
SSI_SCK01239_MARK, SSI_WS01239_MARK,
|
||||
};
|
||||
static const unsigned int ssi1_data_a_pins[] = {
|
||||
/* SDATA */
|
||||
RCAR_GP_PIN(6, 3),
|
||||
};
|
||||
static const unsigned int ssi1_data_a_mux[] = {
|
||||
SSI_SDATA1_A_MARK,
|
||||
};
|
||||
static const unsigned int ssi1_data_b_pins[] = {
|
||||
/* SDATA */
|
||||
RCAR_GP_PIN(5, 12),
|
||||
};
|
||||
static const unsigned int ssi1_data_b_mux[] = {
|
||||
SSI_SDATA1_B_MARK,
|
||||
};
|
||||
static const unsigned int ssi1_ctrl_a_pins[] = {
|
||||
/* SCK, WS */
|
||||
RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
|
||||
};
|
||||
static const unsigned int ssi1_ctrl_a_mux[] = {
|
||||
SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
|
||||
};
|
||||
static const unsigned int ssi1_ctrl_b_pins[] = {
|
||||
/* SCK, WS */
|
||||
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
|
||||
};
|
||||
static const unsigned int ssi1_ctrl_b_mux[] = {
|
||||
SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
|
||||
};
|
||||
static const unsigned int ssi2_data_a_pins[] = {
|
||||
/* SDATA */
|
||||
RCAR_GP_PIN(6, 4),
|
||||
};
|
||||
static const unsigned int ssi2_data_a_mux[] = {
|
||||
SSI_SDATA2_A_MARK,
|
||||
};
|
||||
static const unsigned int ssi2_data_b_pins[] = {
|
||||
/* SDATA */
|
||||
RCAR_GP_PIN(5, 13),
|
||||
};
|
||||
static const unsigned int ssi2_data_b_mux[] = {
|
||||
SSI_SDATA2_B_MARK,
|
||||
};
|
||||
static const unsigned int ssi2_ctrl_a_pins[] = {
|
||||
/* SCK, WS */
|
||||
RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
|
||||
};
|
||||
static const unsigned int ssi2_ctrl_a_mux[] = {
|
||||
SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
|
||||
};
|
||||
static const unsigned int ssi2_ctrl_b_pins[] = {
|
||||
/* SCK, WS */
|
||||
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
|
||||
};
|
||||
static const unsigned int ssi2_ctrl_b_mux[] = {
|
||||
SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
|
||||
};
|
||||
static const unsigned int ssi3_data_pins[] = {
|
||||
/* SDATA */
|
||||
RCAR_GP_PIN(6, 7),
|
||||
};
|
||||
static const unsigned int ssi3_data_mux[] = {
|
||||
SSI_SDATA3_MARK,
|
||||
};
|
||||
static const unsigned int ssi349_ctrl_pins[] = {
|
||||
/* SCK, WS */
|
||||
RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
|
||||
};
|
||||
static const unsigned int ssi349_ctrl_mux[] = {
|
||||
SSI_SCK349_MARK, SSI_WS349_MARK,
|
||||
};
|
||||
static const unsigned int ssi4_data_pins[] = {
|
||||
/* SDATA */
|
||||
RCAR_GP_PIN(6, 10),
|
||||
};
|
||||
static const unsigned int ssi4_data_mux[] = {
|
||||
SSI_SDATA4_MARK,
|
||||
};
|
||||
static const unsigned int ssi4_ctrl_pins[] = {
|
||||
/* SCK, WS */
|
||||
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
|
||||
};
|
||||
static const unsigned int ssi4_ctrl_mux[] = {
|
||||
SSI_SCK4_MARK, SSI_WS4_MARK,
|
||||
};
|
||||
static const unsigned int ssi5_data_pins[] = {
|
||||
/* SDATA */
|
||||
RCAR_GP_PIN(6, 13),
|
||||
};
|
||||
static const unsigned int ssi5_data_mux[] = {
|
||||
SSI_SDATA5_MARK,
|
||||
};
|
||||
static const unsigned int ssi5_ctrl_pins[] = {
|
||||
/* SCK, WS */
|
||||
RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
|
||||
};
|
||||
static const unsigned int ssi5_ctrl_mux[] = {
|
||||
SSI_SCK5_MARK, SSI_WS5_MARK,
|
||||
};
|
||||
static const unsigned int ssi6_data_pins[] = {
|
||||
/* SDATA */
|
||||
RCAR_GP_PIN(6, 16),
|
||||
};
|
||||
static const unsigned int ssi6_data_mux[] = {
|
||||
SSI_SDATA6_MARK,
|
||||
};
|
||||
static const unsigned int ssi6_ctrl_pins[] = {
|
||||
/* SCK, WS */
|
||||
RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
|
||||
};
|
||||
static const unsigned int ssi6_ctrl_mux[] = {
|
||||
SSI_SCK6_MARK, SSI_WS6_MARK,
|
||||
};
|
||||
static const unsigned int ssi7_data_pins[] = {
|
||||
/* SDATA */
|
||||
RCAR_GP_PIN(6, 19),
|
||||
};
|
||||
static const unsigned int ssi7_data_mux[] = {
|
||||
SSI_SDATA7_MARK,
|
||||
};
|
||||
static const unsigned int ssi78_ctrl_pins[] = {
|
||||
/* SCK, WS */
|
||||
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
|
||||
};
|
||||
static const unsigned int ssi78_ctrl_mux[] = {
|
||||
SSI_SCK78_MARK, SSI_WS78_MARK,
|
||||
};
|
||||
static const unsigned int ssi8_data_pins[] = {
|
||||
/* SDATA */
|
||||
RCAR_GP_PIN(6, 20),
|
||||
};
|
||||
static const unsigned int ssi8_data_mux[] = {
|
||||
SSI_SDATA8_MARK,
|
||||
};
|
||||
static const unsigned int ssi9_data_a_pins[] = {
|
||||
/* SDATA */
|
||||
RCAR_GP_PIN(6, 21),
|
||||
};
|
||||
static const unsigned int ssi9_data_a_mux[] = {
|
||||
SSI_SDATA9_A_MARK,
|
||||
};
|
||||
static const unsigned int ssi9_data_b_pins[] = {
|
||||
/* SDATA */
|
||||
RCAR_GP_PIN(5, 14),
|
||||
};
|
||||
static const unsigned int ssi9_data_b_mux[] = {
|
||||
SSI_SDATA9_B_MARK,
|
||||
};
|
||||
static const unsigned int ssi9_ctrl_a_pins[] = {
|
||||
/* SCK, WS */
|
||||
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
|
||||
};
|
||||
static const unsigned int ssi9_ctrl_a_mux[] = {
|
||||
SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
|
||||
};
|
||||
static const unsigned int ssi9_ctrl_b_pins[] = {
|
||||
/* SCK, WS */
|
||||
RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
|
||||
};
|
||||
static const unsigned int ssi9_ctrl_b_mux[] = {
|
||||
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(audio_clk_a_a),
|
||||
SH_PFC_PIN_GROUP(audio_clk_a_b),
|
||||
SH_PFC_PIN_GROUP(audio_clk_a_c),
|
||||
SH_PFC_PIN_GROUP(audio_clk_b_a),
|
||||
SH_PFC_PIN_GROUP(audio_clk_b_b),
|
||||
SH_PFC_PIN_GROUP(audio_clk_c_a),
|
||||
SH_PFC_PIN_GROUP(audio_clk_c_b),
|
||||
SH_PFC_PIN_GROUP(audio_clkout_a),
|
||||
SH_PFC_PIN_GROUP(audio_clkout_b),
|
||||
SH_PFC_PIN_GROUP(audio_clkout_c),
|
||||
SH_PFC_PIN_GROUP(audio_clkout_d),
|
||||
SH_PFC_PIN_GROUP(audio_clkout1_a),
|
||||
SH_PFC_PIN_GROUP(audio_clkout1_b),
|
||||
SH_PFC_PIN_GROUP(audio_clkout2_a),
|
||||
SH_PFC_PIN_GROUP(audio_clkout2_b),
|
||||
SH_PFC_PIN_GROUP(audio_clkout3_a),
|
||||
SH_PFC_PIN_GROUP(audio_clkout3_b),
|
||||
SH_PFC_PIN_GROUP(avb_link),
|
||||
SH_PFC_PIN_GROUP(avb_magic),
|
||||
SH_PFC_PIN_GROUP(avb_phy_int),
|
||||
SH_PFC_PIN_GROUP(avb_mdc),
|
||||
SH_PFC_PIN_GROUP(avb_mii),
|
||||
SH_PFC_PIN_GROUP(avb_avtp_pps),
|
||||
SH_PFC_PIN_GROUP(avb_avtp_match_a),
|
||||
SH_PFC_PIN_GROUP(avb_avtp_capture_a),
|
||||
@ -3565,6 +4003,19 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(msiof3_ss2_e),
|
||||
SH_PFC_PIN_GROUP(msiof3_txd_e),
|
||||
SH_PFC_PIN_GROUP(msiof3_rxd_e),
|
||||
SH_PFC_PIN_GROUP(pwm0),
|
||||
SH_PFC_PIN_GROUP(pwm1_a),
|
||||
SH_PFC_PIN_GROUP(pwm1_b),
|
||||
SH_PFC_PIN_GROUP(pwm2_a),
|
||||
SH_PFC_PIN_GROUP(pwm2_b),
|
||||
SH_PFC_PIN_GROUP(pwm3_a),
|
||||
SH_PFC_PIN_GROUP(pwm3_b),
|
||||
SH_PFC_PIN_GROUP(pwm4_a),
|
||||
SH_PFC_PIN_GROUP(pwm4_b),
|
||||
SH_PFC_PIN_GROUP(pwm5_a),
|
||||
SH_PFC_PIN_GROUP(pwm5_b),
|
||||
SH_PFC_PIN_GROUP(pwm6_a),
|
||||
SH_PFC_PIN_GROUP(pwm6_b),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
SH_PFC_PIN_GROUP(scif0_clk),
|
||||
SH_PFC_PIN_GROUP(scif0_ctrl),
|
||||
@ -3620,6 +4071,51 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(sdhi3_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi3_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi3_ds),
|
||||
SH_PFC_PIN_GROUP(ssi0_data),
|
||||
SH_PFC_PIN_GROUP(ssi01239_ctrl),
|
||||
SH_PFC_PIN_GROUP(ssi1_data_a),
|
||||
SH_PFC_PIN_GROUP(ssi1_data_b),
|
||||
SH_PFC_PIN_GROUP(ssi1_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(ssi1_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(ssi2_data_a),
|
||||
SH_PFC_PIN_GROUP(ssi2_data_b),
|
||||
SH_PFC_PIN_GROUP(ssi2_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(ssi2_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(ssi3_data),
|
||||
SH_PFC_PIN_GROUP(ssi349_ctrl),
|
||||
SH_PFC_PIN_GROUP(ssi4_data),
|
||||
SH_PFC_PIN_GROUP(ssi4_ctrl),
|
||||
SH_PFC_PIN_GROUP(ssi5_data),
|
||||
SH_PFC_PIN_GROUP(ssi5_ctrl),
|
||||
SH_PFC_PIN_GROUP(ssi6_data),
|
||||
SH_PFC_PIN_GROUP(ssi6_ctrl),
|
||||
SH_PFC_PIN_GROUP(ssi7_data),
|
||||
SH_PFC_PIN_GROUP(ssi78_ctrl),
|
||||
SH_PFC_PIN_GROUP(ssi8_data),
|
||||
SH_PFC_PIN_GROUP(ssi9_data_a),
|
||||
SH_PFC_PIN_GROUP(ssi9_data_b),
|
||||
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
|
||||
};
|
||||
|
||||
static const char * const audio_clk_groups[] = {
|
||||
"audio_clk_a_a",
|
||||
"audio_clk_a_b",
|
||||
"audio_clk_a_c",
|
||||
"audio_clk_b_a",
|
||||
"audio_clk_b_b",
|
||||
"audio_clk_c_a",
|
||||
"audio_clk_c_b",
|
||||
"audio_clkout_a",
|
||||
"audio_clkout_b",
|
||||
"audio_clkout_c",
|
||||
"audio_clkout_d",
|
||||
"audio_clkout1_a",
|
||||
"audio_clkout1_b",
|
||||
"audio_clkout2_a",
|
||||
"audio_clkout2_b",
|
||||
"audio_clkout3_a",
|
||||
"audio_clkout3_b",
|
||||
};
|
||||
|
||||
static const char * const avb_groups[] = {
|
||||
@ -3627,6 +4123,7 @@ static const char * const avb_groups[] = {
|
||||
"avb_magic",
|
||||
"avb_phy_int",
|
||||
"avb_mdc",
|
||||
"avb_mii",
|
||||
"avb_avtp_pps",
|
||||
"avb_avtp_match_a",
|
||||
"avb_avtp_capture_a",
|
||||
@ -3879,6 +4376,40 @@ static const char * const msiof3_groups[] = {
|
||||
"msiof3_rxd_e",
|
||||
};
|
||||
|
||||
static const char * const pwm0_groups[] = {
|
||||
"pwm0",
|
||||
};
|
||||
|
||||
static const char * const pwm1_groups[] = {
|
||||
"pwm1_a",
|
||||
"pwm1_b",
|
||||
};
|
||||
|
||||
static const char * const pwm2_groups[] = {
|
||||
"pwm2_a",
|
||||
"pwm2_b",
|
||||
};
|
||||
|
||||
static const char * const pwm3_groups[] = {
|
||||
"pwm3_a",
|
||||
"pwm3_b",
|
||||
};
|
||||
|
||||
static const char * const pwm4_groups[] = {
|
||||
"pwm4_a",
|
||||
"pwm4_b",
|
||||
};
|
||||
|
||||
static const char * const pwm5_groups[] = {
|
||||
"pwm5_a",
|
||||
"pwm5_b",
|
||||
};
|
||||
|
||||
static const char * const pwm6_groups[] = {
|
||||
"pwm6_a",
|
||||
"pwm6_b",
|
||||
};
|
||||
|
||||
static const char * const scif0_groups[] = {
|
||||
"scif0_data",
|
||||
"scif0_clk",
|
||||
@ -3967,7 +4498,36 @@ static const char * const sdhi3_groups[] = {
|
||||
"sdhi3_ds",
|
||||
};
|
||||
|
||||
static const char * const ssi_groups[] = {
|
||||
"ssi0_data",
|
||||
"ssi01239_ctrl",
|
||||
"ssi1_data_a",
|
||||
"ssi1_data_b",
|
||||
"ssi1_ctrl_a",
|
||||
"ssi1_ctrl_b",
|
||||
"ssi2_data_a",
|
||||
"ssi2_data_b",
|
||||
"ssi2_ctrl_a",
|
||||
"ssi2_ctrl_b",
|
||||
"ssi3_data",
|
||||
"ssi349_ctrl",
|
||||
"ssi4_data",
|
||||
"ssi4_ctrl",
|
||||
"ssi5_data",
|
||||
"ssi5_ctrl",
|
||||
"ssi6_data",
|
||||
"ssi6_ctrl",
|
||||
"ssi7_data",
|
||||
"ssi78_ctrl",
|
||||
"ssi8_data",
|
||||
"ssi9_data_a",
|
||||
"ssi9_data_b",
|
||||
"ssi9_ctrl_a",
|
||||
"ssi9_ctrl_b",
|
||||
};
|
||||
|
||||
static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(audio_clk),
|
||||
SH_PFC_FUNCTION(avb),
|
||||
SH_PFC_FUNCTION(can0),
|
||||
SH_PFC_FUNCTION(can1),
|
||||
@ -3991,6 +4551,13 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(msiof1),
|
||||
SH_PFC_FUNCTION(msiof2),
|
||||
SH_PFC_FUNCTION(msiof3),
|
||||
SH_PFC_FUNCTION(pwm0),
|
||||
SH_PFC_FUNCTION(pwm1),
|
||||
SH_PFC_FUNCTION(pwm2),
|
||||
SH_PFC_FUNCTION(pwm3),
|
||||
SH_PFC_FUNCTION(pwm4),
|
||||
SH_PFC_FUNCTION(pwm5),
|
||||
SH_PFC_FUNCTION(pwm6),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
SH_PFC_FUNCTION(scif2),
|
||||
@ -4002,6 +4569,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(sdhi1),
|
||||
SH_PFC_FUNCTION(sdhi2),
|
||||
SH_PFC_FUNCTION(sdhi3),
|
||||
SH_PFC_FUNCTION(ssi),
|
||||
};
|
||||
|
||||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
@ -4775,8 +5343,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
{ RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
|
||||
{ RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
|
||||
{ RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
|
||||
{ RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */
|
||||
{ RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */
|
||||
{ RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
|
||||
{ RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
|
||||
{ RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
|
||||
{ RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
|
||||
} },
|
||||
@ -5022,8 +5590,8 @@ static const struct sh_pfc_bias_info bias_info[] = {
|
||||
{ RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
|
||||
{ RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
|
||||
{ RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
|
||||
{ RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
|
||||
{ RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
|
||||
{ RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */
|
||||
{ RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */
|
||||
{ RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
|
||||
{ RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
|
||||
{ RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
|
||||
|
||||
@ -259,6 +259,8 @@ struct sh_pfc_soc_info {
|
||||
extern const struct sh_pfc_soc_info emev2_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user