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drm/i915/psr: Use PSR2 macro for PSR2

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Cosmetic change.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180328223046.16125-7-jose.souza@intel.com
This commit is contained in:
José Roberto de Souza 2018-03-28 15:30:43 -07:00 committed by Rodrigo Vivi
parent 95f28d2ec7
commit fe36181be3
2 changed files with 3 additions and 2 deletions
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3
drivers/gpu/drm/i915/i915_reg.h
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@ -4069,8 +4069,9 @@ enum {
#define EDP_PSR2_TP2_TIME_MASK (3<<8) #define EDP_PSR2_TP2_TIME_MASK (3<<8)
#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4) #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
#define EDP_PSR2_IDLE_MASK 0xf
#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a)<<4) #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a)<<4)
#define EDP_PSR2_IDLE_FRAME_MASK 0xf
#define EDP_PSR2_IDLE_FRAME_SHIFT 0
#define EDP_PSR2_STATUS _MMIO(0x6f940) #define EDP_PSR2_STATUS _MMIO(0x6f940)
#define EDP_PSR2_STATUS_STATE_MASK (0xf<<28) #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)

2
drivers/gpu/drm/i915/intel_psr.c
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@ -382,7 +382,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
uint32_t val; uint32_t val;
uint8_t sink_latency; uint8_t sink_latency;
val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
/* FIXME: selective update is probably totally broken because it doesn't /* FIXME: selective update is probably totally broken because it doesn't
* mesh at all with our frontbuffer tracking. And the hw alone isn't * mesh at all with our frontbuffer tracking. And the hw alone isn't