forked from Minki/linux
powerpc/powernv: Reset root port in firmware
Resetting root port has more stuff to do than that for PCIe switch
ports and we should have resetting root port done in firmware instead
of the kernel itself. The problem was introduced by commit 5b2e198e
("powerpc/powernv: Rework EEH reset").
Cc: linux-stable <stable@vger.kernel.org>
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
parent
54f112a383
commit
fd5cee7ce8
@ -510,12 +510,10 @@ static int ioda_eeh_reset(struct eeh_pe *pe, int option)
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int ret;
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int ret;
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/*
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/*
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* The rules applied to reset, either fundamental or hot reset:
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* For PHB reset, we always have complete reset. For those PEs whose
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*
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* primary bus derived from root complex (root bus) or root port
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* We always reset the direct upstream bridge of the PE. If the
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* (usually bus#1), we apply hot or fundamental reset on the root port.
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* direct upstream bridge isn't root bridge, we always take hot
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* For other PEs, we always have hot reset on the PE primary bus.
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* reset no matter what option (fundamental or hot) is. Otherwise,
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* we should do the reset according to the required option.
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*
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*
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* Here, we have different design to pHyp, which always clear the
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* Here, we have different design to pHyp, which always clear the
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* frozen state during PE reset. However, the good idea here from
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* frozen state during PE reset. However, the good idea here from
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@ -529,7 +527,8 @@ static int ioda_eeh_reset(struct eeh_pe *pe, int option)
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ret = ioda_eeh_phb_reset(hose, option);
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ret = ioda_eeh_phb_reset(hose, option);
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} else {
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} else {
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bus = eeh_pe_bus_get(pe);
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bus = eeh_pe_bus_get(pe);
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if (pci_is_root_bus(bus))
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if (pci_is_root_bus(bus) ||
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pci_is_root_bus(bus->parent))
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ret = ioda_eeh_root_reset(hose, option);
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ret = ioda_eeh_root_reset(hose, option);
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else
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else
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ret = ioda_eeh_bridge_reset(bus->self, option);
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ret = ioda_eeh_bridge_reset(bus->self, option);
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