forked from Minki/linux
drm/i915: Rip out legacy page_flip completion/irq handling
All these races and things are now solved through the vblank evasion trick, plus event handling is done using normal vblank even processing and drm_crtc_arm_vblank_event. We can get rid of all this complexity. Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170720175754.30751-5-daniel.vetter@ffwll.ch
This commit is contained in:
Daniel Vetter
parent
a5ec7fe81a
commit
fd3a40242e
@ -1708,18 +1708,6 @@ static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
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}
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}
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static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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{
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bool ret;
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ret = drm_handle_vblank(&dev_priv->drm, pipe);
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if (ret)
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intel_finish_page_flip_mmio(dev_priv, pipe);
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return ret;
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}
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static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
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u32 iir, u32 pipe_stats[I915_MAX_PIPES])
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{
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@ -1784,12 +1772,8 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
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enum pipe pipe;
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for_each_pipe(dev_priv, pipe) {
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if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
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intel_pipe_handle_vblank(dev_priv, pipe))
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intel_check_page_flip(dev_priv, pipe);
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if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
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intel_finish_page_flip_cs(dev_priv, pipe);
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if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
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drm_handle_vblank(&dev_priv->drm, pipe);
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if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
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i9xx_pipe_crc_irq_handler(dev_priv, pipe);
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@ -2241,19 +2225,14 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
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DRM_ERROR("Poison interrupt\n");
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for_each_pipe(dev_priv, pipe) {
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if (de_iir & DE_PIPE_VBLANK(pipe) &&
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intel_pipe_handle_vblank(dev_priv, pipe))
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intel_check_page_flip(dev_priv, pipe);
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if (de_iir & DE_PIPE_VBLANK(pipe))
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drm_handle_vblank(&dev_priv->drm, pipe);
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if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
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intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
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if (de_iir & DE_PIPE_CRC_DONE(pipe))
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i9xx_pipe_crc_irq_handler(dev_priv, pipe);
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/* plane/pipes map 1:1 on ilk+ */
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if (de_iir & DE_PLANE_FLIP_DONE(pipe))
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intel_finish_page_flip_cs(dev_priv, pipe);
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}
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/* check event from PCH */
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@ -2292,13 +2271,8 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
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intel_opregion_asle_intr(dev_priv);
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for_each_pipe(dev_priv, pipe) {
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if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
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intel_pipe_handle_vblank(dev_priv, pipe))
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intel_check_page_flip(dev_priv, pipe);
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/* plane/pipes map 1:1 on ilk+ */
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if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
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intel_finish_page_flip_cs(dev_priv, pipe);
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if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
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drm_handle_vblank(&dev_priv->drm, pipe);
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}
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/* check event from PCH */
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@ -2479,7 +2453,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
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}
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for_each_pipe(dev_priv, pipe) {
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u32 flip_done, fault_errors;
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u32 fault_errors;
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if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
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continue;
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@ -2493,18 +2467,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
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ret = IRQ_HANDLED;
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I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
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if (iir & GEN8_PIPE_VBLANK &&
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intel_pipe_handle_vblank(dev_priv, pipe))
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intel_check_page_flip(dev_priv, pipe);
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flip_done = iir;
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if (INTEL_GEN(dev_priv) >= 9)
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flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
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else
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flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
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if (flip_done)
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intel_finish_page_flip_cs(dev_priv, pipe);
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if (iir & GEN8_PIPE_VBLANK)
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drm_handle_vblank(&dev_priv->drm, pipe);
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if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
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hsw_pipe_crc_irq_handler(dev_priv, pipe);
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@ -3675,34 +3639,6 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
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/*
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* Returns true when a page flip has completed.
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*/
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static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
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int plane, int pipe, u32 iir)
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{
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u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
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if (!intel_pipe_handle_vblank(dev_priv, pipe))
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return false;
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if ((iir & flip_pending) == 0)
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goto check_page_flip;
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/* We detect FlipDone by looking for the change in PendingFlip from '1'
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* to '0' on the following vblank, i.e. IIR has the Pendingflip
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* asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
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* the flip is completed (no longer pending). Since this doesn't raise
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* an interrupt per se, we watch for the change at vblank.
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*/
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if (I915_READ16(ISR) & flip_pending)
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goto check_page_flip;
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intel_finish_page_flip_cs(dev_priv, pipe);
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return true;
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check_page_flip:
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intel_check_page_flip(dev_priv, pipe);
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return false;
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}
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static irqreturn_t i8xx_irq_handler(int irq, void *arg)
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{
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struct drm_device *dev = arg;
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@ -3710,9 +3646,6 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
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u16 iir, new_iir;
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u32 pipe_stats[2];
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int pipe;
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u16 flip_mask =
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I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
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I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
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irqreturn_t ret;
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if (!intel_irqs_enabled(dev_priv))
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@ -3726,7 +3659,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
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if (iir == 0)
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goto out;
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while (iir & ~flip_mask) {
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while (iir) {
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/* Can't rely on pipestat interrupt bit in iir as it might
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* have been cleared after the pipestat interrupt was received.
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* It doesn't set the bit in iir again, but it still produces
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@ -3748,7 +3681,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
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}
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spin_unlock(&dev_priv->irq_lock);
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I915_WRITE16(IIR, iir & ~flip_mask);
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I915_WRITE16(IIR, iir);
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new_iir = I915_READ16(IIR); /* Flush posted writes */
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if (iir & I915_USER_INTERRUPT)
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@ -3759,9 +3692,8 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
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if (HAS_FBC(dev_priv))
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plane = !plane;
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if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
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i8xx_handle_vblank(dev_priv, plane, pipe, iir))
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flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
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if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
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drm_handle_vblank(&dev_priv->drm, pipe);
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if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
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i9xx_pipe_crc_irq_handler(dev_priv, pipe);
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@ -3861,45 +3793,11 @@ static int i915_irq_postinstall(struct drm_device *dev)
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return 0;
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}
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/*
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* Returns true when a page flip has completed.
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*/
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static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
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int plane, int pipe, u32 iir)
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{
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u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
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if (!intel_pipe_handle_vblank(dev_priv, pipe))
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return false;
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if ((iir & flip_pending) == 0)
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goto check_page_flip;
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/* We detect FlipDone by looking for the change in PendingFlip from '1'
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* to '0' on the following vblank, i.e. IIR has the Pendingflip
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* asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
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* the flip is completed (no longer pending). Since this doesn't raise
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* an interrupt per se, we watch for the change at vblank.
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*/
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if (I915_READ(ISR) & flip_pending)
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goto check_page_flip;
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intel_finish_page_flip_cs(dev_priv, pipe);
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return true;
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check_page_flip:
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intel_check_page_flip(dev_priv, pipe);
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return false;
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}
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static irqreturn_t i915_irq_handler(int irq, void *arg)
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{
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struct drm_device *dev = arg;
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struct drm_i915_private *dev_priv = to_i915(dev);
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u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
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u32 flip_mask =
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I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
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I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
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int pipe, ret = IRQ_NONE;
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if (!intel_irqs_enabled(dev_priv))
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@ -3910,7 +3808,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
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iir = I915_READ(IIR);
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do {
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bool irq_received = (iir & ~flip_mask) != 0;
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bool irq_received = (iir) != 0;
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bool blc_event = false;
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/* Can't rely on pipestat interrupt bit in iir as it might
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@ -3945,7 +3843,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
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i9xx_hpd_irq_handler(dev_priv, hotplug_status);
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}
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I915_WRITE(IIR, iir & ~flip_mask);
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I915_WRITE(IIR, iir);
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new_iir = I915_READ(IIR); /* Flush posted writes */
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if (iir & I915_USER_INTERRUPT)
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@ -3956,9 +3854,8 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
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if (HAS_FBC(dev_priv))
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plane = !plane;
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if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
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i915_handle_vblank(dev_priv, plane, pipe, iir))
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flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
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if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
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drm_handle_vblank(&dev_priv->drm, pipe);
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if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
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blc_event = true;
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@ -3991,7 +3888,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
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*/
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ret = IRQ_HANDLED;
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iir = new_iir;
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} while (iir & ~flip_mask);
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} while (iir);
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enable_rpm_wakeref_asserts(dev_priv);
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@ -4126,9 +4023,6 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
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u32 iir, new_iir;
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u32 pipe_stats[I915_MAX_PIPES];
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int ret = IRQ_NONE, pipe;
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u32 flip_mask =
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I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
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I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
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if (!intel_irqs_enabled(dev_priv))
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return IRQ_NONE;
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@ -4139,7 +4033,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
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iir = I915_READ(IIR);
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for (;;) {
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bool irq_received = (iir & ~flip_mask) != 0;
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bool irq_received = (iir) != 0;
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bool blc_event = false;
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/* Can't rely on pipestat interrupt bit in iir as it might
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@ -4177,7 +4071,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
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i9xx_hpd_irq_handler(dev_priv, hotplug_status);
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}
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I915_WRITE(IIR, iir & ~flip_mask);
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I915_WRITE(IIR, iir);
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new_iir = I915_READ(IIR); /* Flush posted writes */
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if (iir & I915_USER_INTERRUPT)
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@ -4186,9 +4080,8 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
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notify_ring(dev_priv->engine[VCS]);
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for_each_pipe(dev_priv, pipe) {
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if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
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i915_handle_vblank(dev_priv, pipe, pipe, iir))
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flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
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if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
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drm_handle_vblank(&dev_priv->drm, pipe);
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if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
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blc_event = true;
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@ -3405,14 +3405,6 @@ static void skylake_disable_primary_plane(struct intel_plane *primary,
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spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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}
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static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
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{
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struct intel_crtc *crtc;
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for_each_intel_crtc(&dev_priv->drm, crtc)
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intel_finish_page_flip_cs(dev_priv, crtc->pipe);
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}
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static int
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__intel_display_resume(struct drm_device *dev,
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struct drm_atomic_state *state,
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@ -3521,13 +3513,6 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
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if (!state)
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goto unlock;
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/*
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* Flips in the rings will be nuked by the reset,
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* so complete all pending flips so that user space
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* will get its events and not get stuck.
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*/
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intel_complete_page_flips(dev_priv);
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dev_priv->modeset_restore_state = NULL;
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/* reset doesn't touch the display */
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@ -10121,140 +10106,6 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
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kfree(intel_crtc);
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}
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/* Is 'a' after or equal to 'b'? */
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static bool g4x_flip_count_after_eq(u32 a, u32 b)
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{
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return !((a - b) & 0x80000000);
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}
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static bool __pageflip_finished_cs(struct intel_crtc *crtc,
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struct intel_flip_work *work)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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if (abort_flip_on_reset(crtc))
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return true;
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/*
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* The relevant registers doen't exist on pre-ctg.
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* As the flip done interrupt doesn't trigger for mmio
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* flips on gmch platforms, a flip count check isn't
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* really needed there. But since ctg has the registers,
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* include it in the check anyway.
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*/
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if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
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return true;
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/*
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* BDW signals flip done immediately if the plane
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* is disabled, even if the plane enable is already
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* armed to occur at the next vblank :(
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*/
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/*
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* A DSPSURFLIVE check isn't enough in case the mmio and CS flips
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* used the same base address. In that case the mmio flip might
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* have completed, but the CS hasn't even executed the flip yet.
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*
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* A flip count check isn't enough as the CS might have updated
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* the base address just after start of vblank, but before we
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* managed to process the interrupt. This means we'd complete the
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* CS flip too soon.
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*
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* Combining both checks should get us a good enough result. It may
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* still happen that the CS flip has been executed, but has not
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* yet actually completed. But in case the base address is the same
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* anyway, we don't really care.
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*/
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return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
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crtc->flip_work->gtt_offset &&
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g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
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crtc->flip_work->flip_count);
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}
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static bool
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__pageflip_finished_mmio(struct intel_crtc *crtc,
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struct intel_flip_work *work)
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{
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/*
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* MMIO work completes when vblank is different from
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* flip_queued_vblank.
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*
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* Reset counter value doesn't matter, this is handled by
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* i915_wait_request finishing early, so no need to handle
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* reset here.
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*/
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return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
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}
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|
||||
static bool pageflip_finished(struct intel_crtc *crtc,
|
||||
struct intel_flip_work *work)
|
||||
{
|
||||
if (!atomic_read(&work->pending))
|
||||
return false;
|
||||
|
||||
smp_rmb();
|
||||
|
||||
if (is_mmio_work(work))
|
||||
return __pageflip_finished_mmio(crtc, work);
|
||||
else
|
||||
return __pageflip_finished_cs(crtc, work);
|
||||
}
|
||||
|
||||
void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
|
||||
{
|
||||
struct drm_device *dev = &dev_priv->drm;
|
||||
struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
|
||||
struct intel_flip_work *work;
|
||||
unsigned long flags;
|
||||
|
||||
/* Ignore early vblank irqs */
|
||||
if (!crtc)
|
||||
return;
|
||||
|
||||
/*
|
||||
* This is called both by irq handlers and the reset code (to complete
|
||||
* lost pageflips) so needs the full irqsave spinlocks.
|
||||
*/
|
||||
spin_lock_irqsave(&dev->event_lock, flags);
|
||||
work = crtc->flip_work;
|
||||
|
||||
if (work != NULL &&
|
||||
!is_mmio_work(work) &&
|
||||
pageflip_finished(crtc, work))
|
||||
page_flip_completed(crtc);
|
||||
|
||||
spin_unlock_irqrestore(&dev->event_lock, flags);
|
||||
}
|
||||
|
||||
void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
|
||||
{
|
||||
struct drm_device *dev = &dev_priv->drm;
|
||||
struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
|
||||
struct intel_flip_work *work;
|
||||
unsigned long flags;
|
||||
|
||||
/* Ignore early vblank irqs */
|
||||
if (!crtc)
|
||||
return;
|
||||
|
||||
/*
|
||||
* This is called both by irq handlers and the reset code (to complete
|
||||
* lost pageflips) so needs the full irqsave spinlocks.
|
||||
*/
|
||||
spin_lock_irqsave(&dev->event_lock, flags);
|
||||
work = crtc->flip_work;
|
||||
|
||||
if (work != NULL &&
|
||||
is_mmio_work(work) &&
|
||||
pageflip_finished(crtc, work))
|
||||
page_flip_completed(crtc);
|
||||
|
||||
spin_unlock_irqrestore(&dev->event_lock, flags);
|
||||
}
|
||||
|
||||
static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
|
||||
struct intel_flip_work *work)
|
||||
{
|
||||
@ -10265,72 +10116,6 @@ static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
|
||||
atomic_set(&work->pending, 1);
|
||||
}
|
||||
|
||||
static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
|
||||
struct intel_crtc *intel_crtc,
|
||||
struct intel_flip_work *work)
|
||||
{
|
||||
u32 addr, vblank;
|
||||
|
||||
if (!atomic_read(&work->pending))
|
||||
return false;
|
||||
|
||||
smp_rmb();
|
||||
|
||||
vblank = intel_crtc_get_vblank_counter(intel_crtc);
|
||||
if (work->flip_ready_vblank == 0) {
|
||||
if (work->flip_queued_req &&
|
||||
!i915_gem_request_completed(work->flip_queued_req))
|
||||
return false;
|
||||
|
||||
work->flip_ready_vblank = vblank;
|
||||
}
|
||||
|
||||
if (vblank - work->flip_ready_vblank < 3)
|
||||
return false;
|
||||
|
||||
/* Potential stall - if we see that the flip has happened,
|
||||
* assume a missed interrupt. */
|
||||
if (INTEL_GEN(dev_priv) >= 4)
|
||||
addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
|
||||
else
|
||||
addr = I915_READ(DSPADDR(intel_crtc->plane));
|
||||
|
||||
/* There is a potential issue here with a false positive after a flip
|
||||
* to the same address. We could address this by checking for a
|
||||
* non-incrementing frame counter.
|
||||
*/
|
||||
return addr == work->gtt_offset;
|
||||
}
|
||||
|
||||
void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
|
||||
{
|
||||
struct drm_device *dev = &dev_priv->drm;
|
||||
struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
|
||||
struct intel_flip_work *work;
|
||||
|
||||
WARN_ON(!in_interrupt());
|
||||
|
||||
if (crtc == NULL)
|
||||
return;
|
||||
|
||||
spin_lock(&dev->event_lock);
|
||||
work = crtc->flip_work;
|
||||
|
||||
if (work != NULL && !is_mmio_work(work) &&
|
||||
__pageflip_stall_check_cs(dev_priv, crtc, work)) {
|
||||
WARN_ONCE(1,
|
||||
"Kicking stuck page flip: queued at %d, now %d\n",
|
||||
work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
|
||||
page_flip_completed(crtc);
|
||||
work = NULL;
|
||||
}
|
||||
|
||||
if (work != NULL && !is_mmio_work(work) &&
|
||||
intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
|
||||
intel_queue_rps_boost_for_request(work->flip_queued_req);
|
||||
spin_unlock(&dev->event_lock);
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_wm_need_update - Check whether watermarks need updating
|
||||
* @plane: drm plane
|
||||
|
||||
@ -1408,9 +1408,6 @@ void intel_unpin_fb_vma(struct i915_vma *vma);
|
||||
struct drm_framebuffer *
|
||||
intel_framebuffer_create(struct drm_i915_gem_object *obj,
|
||||
struct drm_mode_fb_cmd2 *mode_cmd);
|
||||
void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
|
||||
void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
|
||||
void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
|
||||
int intel_prepare_plane_fb(struct drm_plane *plane,
|
||||
struct drm_plane_state *new_state);
|
||||
void intel_cleanup_plane_fb(struct drm_plane *plane,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user