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drm/i915/dp: Register definition for DP compliance register

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DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.

v1: Initial patch.
v2: used pipe instead of port in macro definition. [Manasi]
v3: used trans_offset for offset calculation. [Manasi]
v4: Used MMIO_PIPE for evenly spaced register offset instead
MMIO_PIPE2. [Ville]

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200324051111.29398-1-animesh.manna@intel.com
This commit is contained in:
Animesh Manna 2020-03-24 10:41:11 +05:30 committed by Maarten Lankhorst
parent 75947e39f3
commit fce214aea8
1 changed files with 18 additions and 0 deletions
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18
drivers/gpu/drm/i915/i915_reg.h
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@ -9794,6 +9794,24 @@ enum skl_power_gate {
#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
/* DDI DP Compliance Control */
#define _DDI_DP_COMP_CTL_A 0x605F0
#define _DDI_DP_COMP_CTL_B 0x615F0
#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
/* DDI DP Compliance Pattern */
#define _DDI_DP_COMP_PAT_A 0x605F4
#define _DDI_DP_COMP_PAT_B 0x615F4
#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
/* Sideband Interface (SBI) is programmed indirectly, via
* SBI_ADDR, which contains the register offset; and SBI_DATA,
* which contains the payload */