Merge remote-tracking branches 'spi/topic/fsl-dspi', 'spi/topic/mpc512x', 'spi/topic/mtk', 'spi/topic/oc-tiny' and 'spi/topic/octeon' into spi-next
This commit is contained in:
commit
fc579056af
@ -29,8 +29,11 @@ Required properties:
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muxes clock, and "spi-clk" for the clock gate.
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muxes clock, and "spi-clk" for the clock gate.
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Optional properties:
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Optional properties:
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-cs-gpios: see spi-bus.txt, only required for MT8173.
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- mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi
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- mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi
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controller used, this value should be 0~3, only required for MT8173.
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controller used. This is a array, the element value should be 0~3,
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only required for MT8173.
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0: specify GPIO69,70,71,72 for spi pins.
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0: specify GPIO69,70,71,72 for spi pins.
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1: specify GPIO102,103,104,105 for spi pins.
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1: specify GPIO102,103,104,105 for spi pins.
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2: specify GPIO128,129,130,131 for spi pins.
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2: specify GPIO128,129,130,131 for spi pins.
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@ -49,7 +52,7 @@ spi: spi@1100a000 {
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<&topckgen CLK_TOP_SPI_SEL>,
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<&topckgen CLK_TOP_SPI_SEL>,
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<&pericfg CLK_PERI_SPI0>;
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<&pericfg CLK_PERI_SPI0>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
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mediatek,pad-select = <0>;
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mediatek,pad-select = <1>, <0>;
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status = "disabled";
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status = "disabled";
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};
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};
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@ -315,7 +315,7 @@ config SPI_FSL_SPI
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config SPI_FSL_DSPI
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config SPI_FSL_DSPI
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tristate "Freescale DSPI controller"
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tristate "Freescale DSPI controller"
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select REGMAP_MMIO
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select REGMAP_MMIO
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depends on SOC_VF610 || SOC_LS1021A || COMPILE_TEST
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depends on SOC_VF610 || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
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help
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help
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This enables support for the Freescale DSPI controller in master
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This enables support for the Freescale DSPI controller in master
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mode. VF610 platform uses the controller.
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mode. VF610 platform uses the controller.
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@ -409,9 +409,6 @@ static int dspi_transfer_one_message(struct spi_master *master,
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SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
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SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
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regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
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regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
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dspi->cur_chip->ctar_val);
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dspi->cur_chip->ctar_val);
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if (transfer->speed_hz)
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regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
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dspi->cur_chip->ctar_val);
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trans_mode = dspi->devtype_data->trans_mode;
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trans_mode = dspi->devtype_data->trans_mode;
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switch (trans_mode) {
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switch (trans_mode) {
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@ -302,11 +302,9 @@ static int mpc512x_psc_spi_msg_xfer(struct spi_master *master,
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cs_change = 1;
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cs_change = 1;
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status = 0;
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status = 0;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (t->bits_per_word || t->speed_hz) {
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status = mpc512x_psc_spi_transfer_setup(spi, t);
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status = mpc512x_psc_spi_transfer_setup(spi, t);
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if (status < 0)
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if (status < 0)
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break;
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break;
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}
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if (cs_change)
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if (cs_change)
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mpc512x_psc_spi_activate_cs(spi);
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mpc512x_psc_spi_activate_cs(spi);
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@ -20,6 +20,7 @@
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#include <linux/ioport.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/spi-mt65xx.h>
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#include <linux/platform_data/spi-mt65xx.h>
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#include <linux/pm_runtime.h>
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#include <linux/pm_runtime.h>
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@ -84,7 +85,8 @@ struct mtk_spi_compatible {
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struct mtk_spi {
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struct mtk_spi {
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void __iomem *base;
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void __iomem *base;
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u32 state;
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u32 state;
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u32 pad_sel;
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int pad_num;
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u32 *pad_sel;
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struct clk *parent_clk, *sel_clk, *spi_clk;
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struct clk *parent_clk, *sel_clk, *spi_clk;
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struct spi_transfer *cur_transfer;
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struct spi_transfer *cur_transfer;
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u32 xfer_len;
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u32 xfer_len;
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@ -131,10 +133,28 @@ static void mtk_spi_reset(struct mtk_spi *mdata)
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writel(reg_val, mdata->base + SPI_CMD_REG);
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writel(reg_val, mdata->base + SPI_CMD_REG);
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}
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}
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static void mtk_spi_config(struct mtk_spi *mdata,
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static int mtk_spi_prepare_message(struct spi_master *master,
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struct mtk_chip_config *chip_config)
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struct spi_message *msg)
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{
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{
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u16 cpha, cpol;
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u32 reg_val;
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u32 reg_val;
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struct spi_device *spi = msg->spi;
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struct mtk_chip_config *chip_config = spi->controller_data;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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cpha = spi->mode & SPI_CPHA ? 1 : 0;
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cpol = spi->mode & SPI_CPOL ? 1 : 0;
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reg_val = readl(mdata->base + SPI_CMD_REG);
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if (cpha)
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reg_val |= SPI_CMD_CPHA;
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else
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reg_val &= ~SPI_CMD_CPHA;
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if (cpol)
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reg_val |= SPI_CMD_CPOL;
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else
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reg_val &= ~SPI_CMD_CPOL;
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writel(reg_val, mdata->base + SPI_CMD_REG);
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reg_val = readl(mdata->base + SPI_CMD_REG);
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reg_val = readl(mdata->base + SPI_CMD_REG);
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@ -170,38 +190,8 @@ static void mtk_spi_config(struct mtk_spi *mdata,
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/* pad select */
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/* pad select */
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if (mdata->dev_comp->need_pad_sel)
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if (mdata->dev_comp->need_pad_sel)
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writel(mdata->pad_sel, mdata->base + SPI_PAD_SEL_REG);
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writel(mdata->pad_sel[spi->chip_select],
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}
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mdata->base + SPI_PAD_SEL_REG);
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static int mtk_spi_prepare_message(struct spi_master *master,
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struct spi_message *msg)
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{
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u32 reg_val;
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u8 cpha, cpol;
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struct mtk_chip_config *chip_config;
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struct spi_device *spi = msg->spi;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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cpha = spi->mode & SPI_CPHA ? 1 : 0;
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cpol = spi->mode & SPI_CPOL ? 1 : 0;
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reg_val = readl(mdata->base + SPI_CMD_REG);
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if (cpha)
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reg_val |= SPI_CMD_CPHA;
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else
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reg_val &= ~SPI_CMD_CPHA;
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if (cpol)
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reg_val |= SPI_CMD_CPOL;
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else
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reg_val &= ~SPI_CMD_CPOL;
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writel(reg_val, mdata->base + SPI_CMD_REG);
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chip_config = spi->controller_data;
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if (!chip_config) {
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chip_config = (void *)&mtk_default_chip_info;
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spi->controller_data = chip_config;
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}
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mtk_spi_config(mdata, chip_config);
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return 0;
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return 0;
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}
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}
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@ -413,6 +403,19 @@ static bool mtk_spi_can_dma(struct spi_master *master,
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return xfer->len > MTK_SPI_MAX_FIFO_SIZE;
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return xfer->len > MTK_SPI_MAX_FIFO_SIZE;
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}
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}
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static int mtk_spi_setup(struct spi_device *spi)
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{
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struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
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if (!spi->controller_data)
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spi->controller_data = (void *)&mtk_default_chip_info;
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if (mdata->dev_comp->need_pad_sel)
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gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
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return 0;
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}
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static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
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static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
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{
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{
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u32 cmd, reg_val, cnt;
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u32 cmd, reg_val, cnt;
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@ -484,7 +487,7 @@ static int mtk_spi_probe(struct platform_device *pdev)
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struct mtk_spi *mdata;
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struct mtk_spi *mdata;
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const struct of_device_id *of_id;
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const struct of_device_id *of_id;
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struct resource *res;
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struct resource *res;
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int irq, ret;
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int i, irq, ret;
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master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
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master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
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if (!master) {
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if (!master) {
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@ -500,6 +503,7 @@ static int mtk_spi_probe(struct platform_device *pdev)
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master->prepare_message = mtk_spi_prepare_message;
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master->prepare_message = mtk_spi_prepare_message;
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master->transfer_one = mtk_spi_transfer_one;
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master->transfer_one = mtk_spi_transfer_one;
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master->can_dma = mtk_spi_can_dma;
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master->can_dma = mtk_spi_can_dma;
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master->setup = mtk_spi_setup;
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of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
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of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
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if (!of_id) {
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if (!of_id) {
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@ -514,21 +518,34 @@ static int mtk_spi_probe(struct platform_device *pdev)
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master->flags = SPI_MASTER_MUST_TX;
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master->flags = SPI_MASTER_MUST_TX;
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if (mdata->dev_comp->need_pad_sel) {
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if (mdata->dev_comp->need_pad_sel) {
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ret = of_property_read_u32(pdev->dev.of_node,
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mdata->pad_num = of_property_count_u32_elems(
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"mediatek,pad-select",
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pdev->dev.of_node,
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&mdata->pad_sel);
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"mediatek,pad-select");
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if (ret) {
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if (mdata->pad_num < 0) {
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dev_err(&pdev->dev, "failed to read pad select: %d\n",
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dev_err(&pdev->dev,
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ret);
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"No 'mediatek,pad-select' property\n");
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ret = -EINVAL;
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goto err_put_master;
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goto err_put_master;
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}
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}
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if (mdata->pad_sel > MT8173_SPI_MAX_PAD_SEL) {
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mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
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dev_err(&pdev->dev, "wrong pad-select: %u\n",
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sizeof(u32), GFP_KERNEL);
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mdata->pad_sel);
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if (!mdata->pad_sel) {
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ret = -EINVAL;
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ret = -ENOMEM;
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goto err_put_master;
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goto err_put_master;
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}
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}
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for (i = 0; i < mdata->pad_num; i++) {
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of_property_read_u32_index(pdev->dev.of_node,
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"mediatek,pad-select",
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i, &mdata->pad_sel[i]);
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if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
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dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
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i, mdata->pad_sel[i]);
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ret = -EINVAL;
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goto err_put_master;
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}
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}
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}
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}
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platform_set_drvdata(pdev, master);
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platform_set_drvdata(pdev, master);
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@ -606,6 +623,26 @@ static int mtk_spi_probe(struct platform_device *pdev)
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goto err_put_master;
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goto err_put_master;
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}
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}
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if (mdata->dev_comp->need_pad_sel) {
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if (mdata->pad_num != master->num_chipselect) {
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dev_err(&pdev->dev,
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"pad_num does not match num_chipselect(%d != %d)\n",
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mdata->pad_num, master->num_chipselect);
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ret = -EINVAL;
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goto err_put_master;
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}
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for (i = 0; i < master->num_chipselect; i++) {
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ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
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dev_name(&pdev->dev));
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if (ret) {
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dev_err(&pdev->dev,
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"can't get CS GPIO %i\n", i);
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goto err_put_master;
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}
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}
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}
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return 0;
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return 0;
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err_disable_clk:
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err_disable_clk:
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@ -207,8 +207,7 @@ static int tiny_spi_of_probe(struct platform_device *pdev)
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struct tiny_spi *hw = platform_get_drvdata(pdev);
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struct tiny_spi *hw = platform_get_drvdata(pdev);
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struct device_node *np = pdev->dev.of_node;
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struct device_node *np = pdev->dev.of_node;
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unsigned int i;
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unsigned int i;
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const __be32 *val;
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u32 val;
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int len;
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if (!np)
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if (!np)
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return 0;
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return 0;
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@ -226,13 +225,10 @@ static int tiny_spi_of_probe(struct platform_device *pdev)
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return -ENODEV;
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return -ENODEV;
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}
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}
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hw->bitbang.master->dev.of_node = pdev->dev.of_node;
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hw->bitbang.master->dev.of_node = pdev->dev.of_node;
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val = of_get_property(pdev->dev.of_node,
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if (!of_property_read_u32(np, "clock-frequency", &val))
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"clock-frequency", &len);
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hw->freq = val;
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if (val && len >= sizeof(__be32))
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if (!of_property_read_u32(np, "baud-width", &val))
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hw->freq = be32_to_cpup(val);
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hw->baudwidth = val;
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val = of_get_property(pdev->dev.of_node, "baud-width", &len);
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if (val && len >= sizeof(__be32))
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hw->baudwidth = be32_to_cpup(val);
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return 0;
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return 0;
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}
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}
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#else /* !CONFIG_OF */
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#else /* !CONFIG_OF */
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@ -65,7 +65,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
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cpha = mode & SPI_CPHA;
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cpha = mode & SPI_CPHA;
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cpol = mode & SPI_CPOL;
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cpol = mode & SPI_CPOL;
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speed_hz = xfer->speed_hz ? : spi->max_speed_hz;
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speed_hz = xfer->speed_hz;
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clkdiv = octeon_get_io_clock_rate() / (2 * speed_hz);
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clkdiv = octeon_get_io_clock_rate() / (2 * speed_hz);
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